socModelCreator failed to generate design

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I'm trying to use socModelCreator tool to generate a soc design for ZCU111 RFSoC board. Only changes I'm doing for the default values are changing interpolation and decimation to x2 and setting the number of parallel samples to 8. However, the model created by simulink fails to generate bitfile with the following error in generate IPCore stage:
create_bd_cell: Time (s): cpu = 00:00:13 ; elapsed = 00:00:35 . Memory (MB): peak = 2735.984 ; gain = 328.633 ; free physical = 685 ; free virtual = 92938
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKFBOUT_MULT_F' from '12.000' to '9.625' has been ignored for IP 'clk_wiz_0'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKOUT0_DIVIDE_F' from '9.375' to '9.625' has been ignored for IP 'clk_wiz_0'
ERROR: [BD 5-683] VLNV <analog.com:user:axi_dmac:1.0> is not supported for the current part.
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
while executing
"create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ${DMA_BLK_NAME_MM2S} "
(procedure "create_dma_interconnects" line 14)
invoked from within
"create_dma_interconnects $DMA_BLK_NAME_S2MM $DMA_BLK_NAME_MM2S $MW_AXIS_DATA_WIDTH_LOCAL $MW_AXIS_DATA_WIDTH_LOCAL"
(procedure "create_root_design" line 48)
invoked from within
"create_root_design $RFDC_BLK_NAME "" $MW_AXIS_DATA_WIDTH_LOCAL $MW_FIFO_NUM_BYTES $DUTSynthFreqMHz \
$MW_RFIP_ADC_DECIMATE $MW_RFIP_DAC_INTERPOLATIO..."
(file "/home/udara/Work/test/socModel/soc_prj/vivado_ip_prj/ipcore/mw_rfsoc/tcl_utils/add_system.tcl" line 574)
while executing
"source $mw_hdl_dir/tcl_utils/add_system.tcl"
(file "vivado_custom_block_design.tcl" line 42)
while executing
"source vivado_custom_block_design.tcl"
(file "vivado_create_prj.tcl" line 31)
INFO: [Common 17-206] Exiting Vivado at Wed Mar 30 13:27:30 2022...
Elapsed time is 75.6305 seconds.
What is causing this issue? and how can I fix this? Thank you for your support on this matter.
Best Regards,
Udara

Answers (1)

Sanjay Boorle
Sanjay Boorle on 29 Aug 2022
Vivado has a bug that it will errors out to say an IP does not support Zynq RFSoC family even though the IP says it supports it. The work-around is to also install Zynq Ultrascale+ MPSoC device in the Vivado installation, then the IP works.

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