how to build a chain of a custom VHDL code
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Hi,
let's say I have a custom, hand-written VHDL code named "buffer.vhd", that have one boolean input and one boolean output.
I'd like to build with HDL coder, a wrapper code named "chain_of_buffer.vhd", that have one boolean input and one boolean output, and that contains n instances of "buffer.vhd" block, connected in series with each other. An additional port should be present to select the number of instances of the subsystem.
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1306570/image.png)
What is the most efficient way to do it?
I tried to understand examples about blackbox and for each subsystem but they are too much complicated for me.
I'm trying to bypass the issue discussed here https://it.mathworks.com/matlabcentral/answers/1916230-generating-asynchronous-delays-with-hdl-coder-in-simulink and realize a model of an asynchronous logic for third party simulator testbenches.
Thank you
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Vanshika Vaishnav
il 9 Mar 2023
Here are some guidance for required model,refer the below mentioned documentations:-
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