Kindly help me in finding the error

Hi

kindly help me in finding the error in the code.i was trying to implement an adaptive filter whose step size is varying according to the equation.i get the output ,but i see that the step size as 'zzzzz' which means it is not connected

`timescale 1ns / 1ps

module adder(A,B,sum);
parameter N=32;
input signed [N-1:0] A;
input signed [N-1:0] B;
output signed [N-1:0] sum;
assign sum = A+B;
endmodule

module multiplier(A,B,sum,clk);
parameter N=32;
input clk;
input signed [N-1:0] A;
input signed [N-1:0] B;
output signed [N-1:0] sum;
reg signed [N-1:0]z;
integer i;
always@(posedge clk)
begin
z=0;
for (i=0;i<32;i=i+1)
begin
if (i!=32'd31)
 if (B[i]==1'b1)
   z=z+(A<<i);
else
 if (B[i]==1'b1)
   z=z-(A<<i);
end
end
assign sum=z;
endmodule



module Delay(clk,clr,in,out);
parameter N=32;
input clk,clr;
input signed [N-1:0] in;
output reg signed [N-1:0] out;
always@(posedge clk)
begin
 if(clr)
  out<=1'b0;
 else
  out<=in;
 end
endmodule


module stepsize_updatea(clk,clr,mu_EVSS,mu,mu_EXTRA,mu_min,mu_max);
parameter N=32;
parameter INT_BITS = 16; // number of integer bits for fixed-point variables
parameter FRAC_BITS = 16; // number of fractional bits for fixed-point variables
input clr,clk;
input signed  mu;
input signed  mu_min;
input signed  mu_max;
input signed  mu_EXTRA;
output reg signed  mu_EVSS;
//input real mu;
//input real mu_min;
//input real mu_max;
//input real mu_EXTRA;
//output real mu_EVSS;
always@(posedge clk)
begin
if (clr)begin
 mu_EVSS<=mu;
end
else if (mu_EVSS<=mu_min)begin
 mu_EVSS<=(mu>>5)+ mu_EXTRA;
end
else if (mu_EVSS>= mu_max)begin
 mu_EVSS<=mu_max;
end else begin
 mu_EVSS<=mu_min;
end
end 
endmodule 
 //mu_EVSS<= (mu > mu_min && mu < mu_max) ? (mu + mu_EXTRA) :
                // (mu <= mu_min) ? (mu >> 5) + mu_EXTRA :
                 //(mu > mu_max) ? mu_max : mu_min

module coeff_update(clk,clr,k0,k1,k2,k3,k4,k5,k6,k7,h0,h1,h2,h3,h4,h5,h6,h7,p0,p1,p2,p3,p4,p5,p6,p7);
parameter N=32;
input clr,clk;
input signed [N-1:0] h0,h1,h2,h3,h4,h5,h6,h7,p0,p1,p2,p3,p4,p5,p6,p7;
output reg signed [N-1:0] k0,k1,k2,k3,k4,k5,k6,k7;

always@(posedge clk)
begin
if(clr) begin
 k0<=h0;
 k1<=h1;
 k2<=h2;
 k3<=h3;
 k4<=h4;
 k5<=h5;
 k6<=h6;
 k7<=h7;
end
else begin
 k0 <= p0;
 k1 <= p1;
 k2 <= p2;
 k3 <= p3;
 k4 <= p4;
 k5 <= p5;
 k6 <= p6;
 k7 <= p7;
 end
end
endmodule
 
module fir_filter_error(clk,clr,X,h0,h1,h2,h3,h4,h5,h6,h7,Y,d);
parameter N=32;
parameter U=10;
input signed [N-1:0] X,h0,h1,h2,h3,h4,h5,h6,h7,d;
output signed [N-1:0] Y;
input clk,clr;
parameter INT_BITS = 16; // number of integer bits for fixed-point variables
parameter FRAC_BITS = 16; // number of fractional bits for fixed-point variables


wire signed [N-1:0] k0,k1,k2,k3,k4,k5,k6,k7,h0,h1,h2,h3,h4,h5,h6,h7,p0,p1,p2,p3,p4,p5,p6,p7;
wire signed [N-1:0] m1_out,d1_out,m2_out,d2_out,m3_out,d3_out,m4_out,d4_out,m5_out,d5_out,m6_out,d6_out,m7_out,d7_out,er_out,m8_out;
wire signed [N-1:0] a1_out,a2_out,a3_out,a4_out,a5_out,a6_out,sum;
wire signed [N-1:0] error;
wire signed  mu_EVSS;
wire signed  mu_min, mu_max,mu,mu_EXTRA;

coeff_update c1(clk,clr,k0,k1,k2,k3,k4,k5,k6,k7,h0,h1,h2,h3,h4,h5,h6,h7,p0,p1,p2,p3,p4,p5,p6,p7);
multiplier m1(X,k0,m1_out,clk);
Delay d1(clk,clr,X,d1_out);
multiplier m2(d1_out,k1,m2_out,clk);
Delay d2(clk,clr,d1_out,d2_out);
multiplier m3(d2_out,k2,m3_out,clk);
Delay d3(clk,clr,d2_out,d3_out);
multiplier m4(d3_out,k3,m4_out,clk);
Delay d4(clk,clr,d3_out,d4_out);
multiplier m5(d4_out,k4,m5_out,clk);
Delay d5(clk,clr,d4_out,d5_out);
multiplier m6(d5_out,k5,m6_out,clk);
Delay d6(clk,clr,d5_out,d6_out);
multiplier m7(d6_out,k6,m7_out,clk);
Delay d7(clk,clr,d6_out,d7_out);
multiplier m8(d7_out,k7,m8_out,clk);
adder a1(m1_out,m2_out,a1_out);
adder a2(a1_out,m3_out,a2_out);
adder a3(a2_out,m4_out,a3_out);
adder a4(a3_out,m5_out,a4_out);
adder a5(a4_out,m6_out,a5_out);
adder a6(a5_out,m7_out,a6_out);
adder a7(a6_out,m8_out,Y);

assign error=d-Y;
stepsize_updatea s1(clk,clr,mu_EVSS,mu,mu_EXTRA,mu_min,mu_max);
multiplier m9(error,mu_EVSS,er_out,clk);

assign p1=k1 + er_out*d1_out;
assign p2=k2 + er_out*d2_out;
assign p3=k3 + er_out*d3_out;
assign p4=k4 + er_out*d4_out;
assign p5=k5 + er_out*d5_out;
assign p6=k6 + er_out*d6_out;
assign p7=k7 + er_out*d7_out;

coeff_update c2(clk,clr,k0,k1,k2,k3,k4,k5,k6,k7,h0,h1,h2,h3,h4,h5,h6,h7,p0,p1,p2,p3,p4,p5,p6,p7);

endmodule

this is the testbench code

`timescale 1ns / 1ps

module adapt_test;
parameter N=32;
parameter INT_BITS = 16; // number of integer bits for fixed-point variables
parameter FRAC_BITS = 16; // number of fractional bits for fixed-point variables


reg clk,clr;
reg signed [N-1:0] h0,h1,h2,h3,h4,h5,h6,h7,d;
reg signed mu;
reg signed mu_min;
reg signed mu_max;
reg signed mu_EXTRA;
wire signed  mu_EVSS;
wire signed [N-1:0] Y;
reg  signed [N-1:0] X;
fir_filter_error main(clk,clr,X,h0,h1,h2,h3,h4,h5,h6,h7,Y,d);
initial begin
clk=1;
clr=1;
h0=32'b0;
h1=32'b01;
h2=32'b10;
h3=32'b11;	
h4=32'b11;
h5=32'b10;
h6=32'b01;
h7=32'b0; 
X=32'd5;
mu = $realtobits(0.025);
mu_min = $realtobits(0.0004);
mu_max = $realtobits(0.025);
mu_EXTRA = $realtobits(1.5e-4);

//d=1500;
d=1100;
//d=300;
//d=70;
#10 clr=0;

#16 X= 32'd6;

#16 X=11;

#1000 $finish;
end


always #5 clk=~clk;

endmodule

[Steven Lord]

This is not MATLAB code. Some quick searching suggests it's Verilog code. But it's not clear to me how this related to any MathWorks product. If you're asking for help debugging some general Verilog code you might have better luck on a discussion forum dedicated to Verilog. If you need help with this in the context of a MathWorks product, please explain the connection (how are you hoping to use this code with that product?)