Simulink automatically generates Verilog. How should it run on FPGA
1 visualizzazione (ultimi 30 giorni)
Mostra commenti meno recenti
I have generated Verolig from part of the module, how do I run this part of Verilog on the FPGA?
“bufen”This subsystem has generated Verilog.And need to measure the time used to run on FPGA.
I plan to run the original algorithm on MATLAB and only this small part on FPGA.
0 Commenti
Risposte (0)
Vedere anche
Categorie
Scopri di più su System on Chip (SoC) in Help Center e File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!