HDL Coder generates RTL code (VHDL, Verilog, SystemVerilog) from the Design Under Test. It can also generate a RTL testbench from the stimulus (source blocks) and response (sink blocks) and generate an RTL testbench. When this testbench is run in an EDA simulator you can confirm if the generated RTL from HDL Coder behaves similar to your original model.
>> sfir_fixed
>> makehdl('sfir_fixed/symmetric_fir')
### Working on the model sfir_fixed
### Generating HDL for sfir_fixed/symmetric_fir
### Using the config set for model sfir_fixed for HDL code generation parameters.
### Running HDL checks on the model 'sfir_fixed'.
### Begin compilation of the model 'sfir_fixed'...
### Working on the model 'sfir_fixed'...
### Working on... GenerateModel
### Begin model generation 'gm_sfir_fixed'...
### Copying DUT to the generated model....
### Model generation complete.
### Generated model saved at hdlsrc\sfir_fixed\gm_sfir_fixed.slx
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as hdlsrc\sfir_fixed\symmetric_fir.vhd.
### Code Generation for 'sfir_fixed' completed.
### Generating HTML files for code generation report at sfir_fixed_codegen_rpt.html
### Creating HDL Code Generation Check Report symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
>> makehdltb('sfir_fixed/symmetric_fir')
### Begin TestBench generation.
### Generating HDL TestBench for 'sfir_fixed/symmetric_fir'.
### Begin compilation of the model 'sfir_fixed'...
### Begin compilation of the model 'gm_sfir_fixed'...
### Begin simulation of the model 'gm_sfir_fixed'...
### Collecting data...
### Generating test bench data file: hdlsrc\sfir_fixed\x_in.dat.
### Generating test bench data file: hdlsrc\sfir_fixed\y_out_expected.dat.
### Generating test bench data file: hdlsrc\sfir_fixed\delayed_xout_expected.dat.
### Working on symmetric_fir_tb as hdlsrc\sfir_fixed\symmetric_fir_tb.vhd.
### Generating package file hdlsrc\sfir_fixed\symmetric_fir_tb_pkg.vhd.
### HDL TestBench generation complete.
>>
During testbench generation the stimulus and response time series data from Simulink simulation is captured in the .dat files. These files are read for reference data when comparing results of Simulink simulation with EDA simulation tool output. Typically one .dat file is generated for each varying input and output signal in Simulink during HDL Coder testbench generation. You can find these files in the output folder.
Hope this helps.
