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Kiran Kintali

Last seen: 3 giorni fa Attivo dal 2011

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Risposto
hdlcoder.optimizeDesign on matlab function
hdlcoder.optimizeDesign runs Simulink to HDL workflow (makehdl) under the hood. I have communicated to the dev team the request...

6 giorni fa | 0

| accettato

Risposto
Simulink HDL coder Shift register SIPO
https://www.mathworks.com/help/hdlcoder/ref/deserializer1d.html You can also consider using the Deserializer block to convert s...

6 giorni fa | 0

Risposto
Is it possible to use different target hardware for implementing deep learning HDL toolbox?
DL HDL ships bitstreams for few reference boards. However, DL HDL IP can be customized to any custom FPGA / ASIC configuration....

6 giorni fa | 1

| accettato

Risposto
why do i get this error?
Please attach files that can run without error. I got an error running the runtrial.m file. You need break the design that nee...

19 giorni fa | 0

Risposto
why do i get this error?
Can you share the design, testbench and the project files? It looks like you are running into some issue with classes during f...

20 giorni fa | 0

Risposto
HDLCoder hdl.ram: Error System Object methods can only be called once
can you please share the design.m, testbench.m and matched_filter.prj files associated with the matched filter design with the c...

22 giorni fa | 0

Risposto
Error while using HDL coder: variable-size matrix type is not supported for HDL code generation
Can you please share design (Inter_func.m) and testbench (Inter_func_tb.m) driving the design with valid inputs and the HDL Code...

22 giorni fa | 0

Risposto
How to solve error Qt: Untested Windows version 6.2 detected! while trying to run create project task in hdl coder ?
Can you share few more details and the error stack you see in the command window? Does this error happen when running AMD/Xil...

23 giorni fa | 0

Risposto
Error while targeting FPGA through simulink, I am trying to implement 'OFDM Transmit and Receive Using Analog Devices AD9361/AD9364' example of MATLAB.
I think you are referring to this demo. OFDM Transmit and Receive Using Analog Devices AD9361/AD9364 https://www.mathworks.c...

29 giorni fa | 0

Risposto
how do i convert this code to HDL using hdl coder?
You can follow these examples in Deep Learning HDL Toolbox. https://www.mathworks.com/help/deep-learning-hdl/examples.html

circa un mese fa | 0

Risposto
Meaning code setDatType RefMdl
This code is looking for specific block name patterns and based on block name assigning output types for the blocks.

circa un mese fa | 0

| accettato

Risposto
[Simulink] get the parameter of the block to be variable in HDL
HDL Coder supports bitshift block with shift length specified via input port. Reach out to technical support on your specific u...

circa un mese fa | 0

Risposto
While running the 'OFDM Transmit and Receive Using Analog Devices AD9361/AD9364' example of MATLAB in Ubuntu, Matlab is crashing while generating the bitstream in HDL Workflow
This is not exected behavior. Can you share more details? Does the folder have HDL code generated? What is the last phase wher...

circa un mese fa | 0

Risposto
Binary Point scaling Vs Slope Bias scaling
HDL Coder currently does not support Slope Bias Scaling for efficiency reasons. Please consider using Binary Point Scaling for b...

circa 2 mesi fa | 0

Risposto
HDL coder implementation of dsp.MovingAverage (moving/block average)
function [y, validOut] = moving_average(x, validIn) %#codegen % Declare persistent array and persistent window size persist...

circa 2 mesi fa | 0

| accettato

Risposto
HDL FIFO accepts three more pushes before signalling full
Can you share the model? thanks

circa 2 mesi fa | 0

| accettato

Risposto
How to create or develop an HDL Verifier function for a specific HDL model
https://www.mathworks.com/help/hdlcoder/ug/verify-sobel-edge-detection-algorithm-in-matlab-to-hdl-workflow.html Example that sh...

2 mesi fa | 0

| accettato

Risposto
HDL Coder fails to generate VHDL, Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\corecomplowering.hpp:97
This is an unexpected error. Can you file a bug report with the support team? There should be a readable error message in case ...

2 mesi fa | 0

Risposto
HDL Coder Variable Size Matrix
Can you share your design and testbench and the project file used? Thanks

2 mesi fa | 0

Risposto
Memory not Initialized in Simulink HDL causing problems in FPGA simulation.
https://www.mathworks.com/help/hdlcoder/ug/rtl-customizations-for-rams.html RTL Customization Parameters for RAMs This page ...

3 mesi fa | 0

Risposto
How to update HDL verifier block when VHDL source changes its port definition?
https://www.mathworks.com/help/hdlverifier/ug/import-hdl-code-for-hdl-cosimulation-block.html does your question refer to this ...

3 mesi fa | 0

Risposto
How to call vhdl program from matlab script
https://www.mathworks.com/help/hdlcoder/ref/hdl.blackbox-system-object.html Integrate Custom HDL Code Into MATLAB Design h...

3 mesi fa | 0

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Risposto
"Detect Increase" causes multiple identical HDL files to be generated with HDL coder
Please consider this option to increase reuse of shared modules. https://www.mathworks.com/help/hdlcoder/ug/generating-reusab...

3 mesi fa | 0

Risposto
Timing error happened when seting series IIR filter in Speedgoat target machine
Please reach out to tech support for guidance on the topic with your model. You can use the workflow to get a high level view o...

3 mesi fa | 0

| accettato

Risposto
What are the implications of using the Derivative block in Simulink?
Prachi, You need to use discrete blocks suitable for HDL code generation. See ex: https://www.mathworks.com/help/simulink/slr...

3 mesi fa | 0

Risposto
How to convert the simscape sample model('ssc_lithium_cell_1RC') to HDL
The model needs to be made Simscape HDL compliant for FPGA/HIL targeting. Watch out this space for guidance on this topic or rea...

3 mesi fa | 0

Risposto
XADC in System Generator/Model Composer for MATLAB
Can you share your Simulink model? Are you trying to utilize HDL Coder workflow advisor IP core generation features? https:/...

4 mesi fa | 0

Risposto
converting fixed point simulink model to zynq 706
https://www.mathworks.com/help/supportpkg/xilinxzynqbasedradio/ug/fpga-targeting-workflow.html Communications Toolbox Support P...

4 mesi fa | 0

Risposto
Mexw64 file not found in matlab foc example
The example ships mex files only for Windows. You need to have necessary products such as Simscape in place to rebuild mex on ot...

4 mesi fa | 0

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Risposto
Synthesis keeps on running for indefinite time on Xilinx RFSOC ZCU111
Please reach out to support if you still run into this issue.

4 mesi fa | 0

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