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Risposto
Error in Setup for HDL Coder Support Package for AMD FPGA and SoC Devices
What version of MATLAB are you using? Have you reached out to tech support?
Error in Setup for HDL Coder Support Package for AMD FPGA and SoC Devices
What version of MATLAB are you using? Have you reached out to tech support?
3 giorni fa | 0
Risposto
Why am I getting the error "found unsupported dynamic matrix type" in HDL Coder R2024b?
Related Thread https://www.mathworks.com/matlabcentral/answers/2179433-why-does-hdl-code-generation-give-errors-when-variable-s...
Why am I getting the error "found unsupported dynamic matrix type" in HDL Coder R2024b?
Related Thread https://www.mathworks.com/matlabcentral/answers/2179433-why-does-hdl-code-generation-give-errors-when-variable-s...
3 giorni fa | 0
Risposto
Discrepancy between Simulink and hdl code behaviour
Could you reach out to tech support for assistance, or alternatively, share your model here? We’d be happy to take a look and pr...
Discrepancy between Simulink and hdl code behaviour
Could you reach out to tech support for assistance, or alternatively, share your model here? We’d be happy to take a look and pr...
circa un mese fa | 0
Risposto
i want to implement 5G NR OFDM system in verilog code using HDL coder
https://www.mathworks.com/help/soc/ug/5g-nr-intro-downlink-signal-detection-rfsoc.html This example shows how to deploy a 5G ...
i want to implement 5G NR OFDM system in verilog code using HDL coder
https://www.mathworks.com/help/soc/ug/5g-nr-intro-downlink-signal-detection-rfsoc.html This example shows how to deploy a 5G ...
circa 2 mesi fa | 0
Risposto
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentati...
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentati...
2 mesi fa | 1
Risposto
Interface with the Deep Learning Processor IP Core (Execution Modes)
System Integration of Deep Learning Processor IP Core This page shows lists the relevant examples https://www.mathworks.com/h...
Interface with the Deep Learning Processor IP Core (Execution Modes)
System Integration of Deep Learning Processor IP Core This page shows lists the relevant examples https://www.mathworks.com/h...
3 mesi fa | 0
| accettato
Risposto
Unable to set Synthesis Attribute on Entity using hdlset_param
In the latest release you should see Block and Block Outputs (Signal) related synthesis attributes specification dialogs and t...
Unable to set Synthesis Attribute on Entity using hdlset_param
In the latest release you should see Block and Block Outputs (Signal) related synthesis attributes specification dialogs and t...
3 mesi fa | 0
Risposto
Unable to set Synthesis Attribute on Entity using hdlset_param
https://www.mathworks.com/help/hdlcoder/ug/configure-custom-synthesis-attributes-for-simulink-blocks.html HDL Coder allows at...
Unable to set Synthesis Attribute on Entity using hdlset_param
https://www.mathworks.com/help/hdlcoder/ug/configure-custom-synthesis-attributes-for-simulink-blocks.html HDL Coder allows at...
3 mesi fa | 0
Risposto
Deep Learning HDL Toolbox with CycloneV SoC board
Can you consider using the example and extend to DE-10 Nao Kit? https://www.mathworks.com/help/hdlcoder/ug/define-and-register-...
Deep Learning HDL Toolbox with CycloneV SoC board
Can you consider using the example and extend to DE-10 Nao Kit? https://www.mathworks.com/help/hdlcoder/ug/define-and-register-...
3 mesi fa | 0
Risposto
Convert a part of simulink model of my project to VHDL or Verilog code for FPGA
https://www.mathworks.com/help/hdlcoder/simscape-to-hdl.html Simscape Hardware-in-the-Loop Workflow Generate HDL code from S...
Convert a part of simulink model of my project to VHDL or Verilog code for FPGA
https://www.mathworks.com/help/hdlcoder/simscape-to-hdl.html Simscape Hardware-in-the-Loop Workflow Generate HDL code from S...
5 mesi fa | 0
Risposto
Is it possible to change Simulink MATLAB Function Block 1-indexing to 0-indexing?
If possible can you share your model and the version of MATLAB you are using? There are few tricks in MATLAB coding and design...
Is it possible to change Simulink MATLAB Function Block 1-indexing to 0-indexing?
If possible can you share your model and the version of MATLAB you are using? There are few tricks in MATLAB coding and design...
6 mesi fa | 0
| accettato
Risposto
Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？
HDL Coder Language Support VHDL, Verilog, and SystemC HLS Language Support The generated HDL code complies with the following...
Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？
HDL Coder Language Support VHDL, Verilog, and SystemC HLS Language Support The generated HDL code complies with the following...
6 mesi fa | 1
Risposto
When I click on "View Code" after generating Verilog code in HDL Coder, the program doesn't respond.
https://www.mathworks.com/help/hdlcoder/ug/traceability-report.html If you are facing issues with code view please reach out to...
When I click on "View Code" after generating Verilog code in HDL Coder, the program doesn't respond.
https://www.mathworks.com/help/hdlcoder/ug/traceability-report.html If you are facing issues with code view please reach out to...
6 mesi fa | 0
| accettato
Risposto
HDL Code Generation Issue – Exceeding IO Pin Count Threshold & MATLAB Freezing
If the generated HDL DUT code results in unreasonable IO, it may eventually lead to failure to meet pin constraint during synthe...
HDL Code Generation Issue – Exceeding IO Pin Count Threshold & MATLAB Freezing
If the generated HDL DUT code results in unreasonable IO, it may eventually lead to failure to meet pin constraint during synthe...
6 mesi fa | 0
Risposto
SigmoidLayer wont work while implementing on ZC706
Thank you for reporting this. Development team is able to reproduce the issue and will post an update soon.
SigmoidLayer wont work while implementing on ZC706
Thank you for reporting this. Development team is able to reproduce the issue and will post an update soon.
6 mesi fa | 0
Risposto
Simulink HDL Coder error when generating
This is an unexpected error handling the if/elseif control structure. Please reach to tech support or share your model here. We ...
Simulink HDL Coder error when generating
This is an unexpected error handling the if/elseif control structure. Please reach to tech support or share your model here. We ...
6 mesi fa | 0
Risposto
How can we tune the Discrete integrator of the HDL Coder for second order generalized integrator for FPGA
Can you share the model here or via tech support? Thanks
How can we tune the Discrete integrator of the HDL Coder for second order generalized integrator for FPGA
Can you share the model here or via tech support? Thanks
6 mesi fa | 0
| accettato
Risposto
Can't register a custom board for the HDL Deep Learning Toolbox
>> Does MATLAB have the option to register a custom board? Yes, You can see the doc here https://www.mathworks.com/help/hdlcode...
Can't register a custom board for the HDL Deep Learning Toolbox
>> Does MATLAB have the option to register a custom board? Yes, You can see the doc here https://www.mathworks.com/help/hdlcode...
6 mesi fa | 0
Risposto
How do I configure HDL Coder so that it recognizes my Vivado version?
Please review this post that is relevant here. https://in.mathworks.com/matlabcentral/answers/518421-which-versions-of-vivado-a...
How do I configure HDL Coder so that it recognizes my Vivado version?
Please review this post that is relevant here. https://in.mathworks.com/matlabcentral/answers/518421-which-versions-of-vivado-a...
6 mesi fa | 0
| accettato
Risposto
What's the most suitable Vivado version for Matlab 2025a
This example shows how to model, partition, and deploy a design that leverages the processor, FPGA, and AI Engines on a Versal d...
What's the most suitable Vivado version for Matlab 2025a
This example shows how to model, partition, and deploy a design that leverages the processor, FPGA, and AI Engines on a Versal d...
7 mesi fa | 0
| accettato
Risposto
MATLAB HDL-Coder: Expression could not be reduced to a constant.
Is hwconst an input variable (creates hardware interface pins) or just a non-tuanble constant parameter passed into the design...
MATLAB HDL-Coder: Expression could not be reduced to a constant.
Is hwconst an input variable (creates hardware interface pins) or just a non-tuanble constant parameter passed into the design...
7 mesi fa | 0
| accettato
Risposto
Troubleshooting Signal Logging in SDI for FPGA Outputs in Speedgoat Motion Control HDL I/O Blockset
Klemen, Thanks for reporting this. Our support team at Speedgoat is reviewing the issue and respond here shortly.
Troubleshooting Signal Logging in SDI for FPGA Outputs in Speedgoat Motion Control HDL I/O Blockset
Klemen, Thanks for reporting this. Our support team at Speedgoat is reviewing the issue and respond here shortly.
7 mesi fa | 1
Risposto
How to resolve unsupported functions in MATLAB HDL Coder?
Happy to assist you with your MATLAB to HDL workflow. Attached is a sample zip file with the code for the attached functions (us...
How to resolve unsupported functions in MATLAB HDL Coder?
Happy to assist you with your MATLAB to HDL workflow. Attached is a sample zip file with the code for the attached functions (us...
7 mesi fa | 0
Risposto
Error evaluating parameter. Dot indexing is not supported for variables of this type.
Can you please share your model here or reach out to tech support? The following message is not expected and a better message ne...
Error evaluating parameter. Dot indexing is not supported for variables of this type.
Can you please share your model here or reach out to tech support? The following message is not expected and a better message ne...
7 mesi fa | 0
Risposto
Matlab for my needs
https://www.mathworks.com/help/hdlcoder/examples.html https://www.mathworks.com/help/hdlcoder/run-and-verify-generated-ip-cor...
Matlab for my needs
https://www.mathworks.com/help/hdlcoder/examples.html https://www.mathworks.com/help/hdlcoder/run-and-verify-generated-ip-cor...
8 mesi fa | 0
Risposto
Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project?
Generating an IP core wrapper for the HDL Coder generated code is the best way to integrate your algorithm into an existing vi...
Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project?
Generating an IP core wrapper for the HDL Coder generated code is the best way to integrate your algorithm into an existing vi...
8 mesi fa | 1
Risposto
Ultra RAM on True Dual Port RAM
Please do attach your sample model as a test case. This is a known issue and HDL Coder R&D team have reported the issue to Viva...
Ultra RAM on True Dual Port RAM
Please do attach your sample model as a test case. This is a known issue and HDL Coder R&D team have reported the issue to Viva...
8 mesi fa | 0
| accettato
Risposto
Using fixed FPGA capacity for a variable number of Simulink signal channels
Have you considered tunable parameter usage in HDL Coder? https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-...
Using fixed FPGA capacity for a variable number of Simulink signal channels
Have you considered tunable parameter usage in HDL Coder? https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-...
9 mesi fa | 0
Risposto
HDL Coder "Error using find Too many input arguments."
Based on the error message this issues seems to be related to report generation infrastructure failure. The issue is resolved in...
HDL Coder "Error using find Too many input arguments."
Based on the error message this issues seems to be related to report generation infrastructure failure. The issue is resolved in...
9 mesi fa | 0
Risposto
Do the additional delays added by adaptive pipeline distroy the alignment between signal paths?
Please share your release. Adaptive Pipelining is an optional feature. When enabled it tries to improve timing of your design. ...
Do the additional delays added by adaptive pipeline distroy the alignment between signal paths?
Please share your release. Adaptive Pipelining is an optional feature. When enabled it tries to improve timing of your design. ...
10 mesi fa | 0
