HDL OFDM Transmitter (whdl/WHDLOFDMTransmitterExample) Issue
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I am using the MATLAB example whdl/WHDLOFDMTransmitterExample. I have successfully generated both the HDL code and the corresponding testbench. However, when I simulate the design in Xilinx Vivado, I do not observe any activity on the output signals txData_re[15:0] and txData_im[15:0].
Despite running the provided testbench, these outputs remain static or undefined in simulation. I would appreciate guidance on any additional clock, reset, or clock-enable handling required in Vivado, or any known issues when simulating this example outside MATLAB.
Thanks in advance for your help.
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Karthik Akula
il 31 Dic 2025
Modificato: Karthik Akula
il 31 Dic 2025
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Make sure if you are able to see activity of the same signals in MATLAB. If not, increase simulation time.
Also please make sure you are running the test bench file in vivado simulation.
If that doesn't solve, then
Need more info on "static or undefined." How do they look like ? Is it possible to give a step by step approach on how you simulated in vivado ? Right from opening the project.
1 Commento
Abdul
il 6 Gen 2026
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