Generate System Verilog (SV) model from matlab/simulink

2 visualizzazioni (ultimi 30 giorni)
Hi,
Does Matlab/Simulink generate the system Verilog (SV) code? If yes, how is it possible? which product generates the SV model? I only want to real number support language in my Mixed signal environment.

Risposte (0)

Categorie

Scopri di più su Signal Processing Toolbox in Help Center e File Exchange

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by