I'm trying to make a simple verilog code by using hdlcoder. so I used as the below script and function. but I came across unexpected result when I run the hdlcoder.
The expected data is all 0 in simulation.
Would you please help me how to resolve this problem?
u = u / 1000;
out = u*dx;
out = floor(out);
Especially, I got the snippet code from calc_fixpt.v But It does not make sense.
assign out_2 = 4'b0000;
always @(posedge clk or negedge reset_x)
begin : out_reg_process
if (reset_x == 1'b0) begin
out_3 <= 4'b0000;
if (enb) begin
out_3 <= out_2;
From this code, the output is always 0. Would you let me know how do resolve this problems?