Dear All,
I'm trying to make a simple verilog code by using hdlcoder. so I used as the below script and function. but I came across unexpected result when I run the hdlcoder.
The expected data is all 0 in simulation.
Would you please help me how to resolve this problem?
-calc.m
function out=calc(u)
dx=1.71;
u = u / 1000;
out = u*dx;
out = floor(out);
end
-test.m
clear
clc
u=3000;
a=calc(u);
u=4000;
a=calc(u);
u=5000;
a=calc(u);
Especially, I got the snippet code from calc_fixpt.v But It does not make sense.
assign out_2 = 4'b0000;
always @(posedge clk or negedge reset_x)
begin : out_reg_process
if (reset_x == 1'b0) begin
out_3 <= 4'b0000;
end
else begin
if (enb) begin
out_3 <= out_2;
end
end
end
From this code, the output is always 0. Would you let me know how do resolve this problems?
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