How to avoid the division operator from hdlcoder?

Dear All,

I've got the below verilog code when I generated with hdlcoder.

    fx = srcX / dstX;

    fy = srcY / dstY;

      always @(srcX, srcY, dstX, dstY, recur, in, AP) begin
      if (dstX == 3'b000) begin
        test_function1_fixpt_tmp = 39'h7FFFFFFFFF;
      end
      else begin
        test_function1_fixpt_cast = {srcX, 24'b000000000000000000000000};
        if (dstX == 31'sd0) begin
          test_function1_fixpt_div_temp = 36'hFFFFFFFFF;
        end
        else begin
          test_function1_fixpt_div_temp = test_function1_fixpt_cast / dstX;
        end
        test_function1_fixpt_tmp = {3'b0, test_function1_fixpt_div_temp};
      end
      test_function1_fixpt_fx = test_function1_fixpt_tmp[33:24];
      //fx = (float)srcX / (float)dstX;  ;

As you can see that used a division operator " /".

But I'm confused quite a bit the output of hdlcoder.

Because I don't want to use "/" a division operator in RTL code, because utilization problem and Design Compiler and Xilinx VIVADO can not synthesize divider problem.

So I want to resolve this problem with another different way instead of "/".

What am I supposed to do to resolve this problem?

 # update

I came across some relative posting as the below when I googling, But In my 2017B matlab version can't find any options. Would you please help and let me know how to resolve this problem?

"The RecipNewton implementation is a HDL Coder option on the Product block. You can reach the HDL Block Options on any HDL-supported block by right-clicking on the block in your model and choosing "HDL Code->HDL Block Properties...". On the Product block, you can then change the 'Architecture' field from the default 'Linear' to 'RecipNewton'. The RecipNewton method is only valid when the block is in division mode; HDL Coder will error out should you choose this architecture when the block is configured for multiplication.

The architecture field describes how the HDL code will be generated for the block. It does not affect Simulink simulation. If the implementation introduces latency, as the RecipNewton architecture can, HDL Coder will notify you of the additional latency that has been inserted. The generated HDL testbench will be automatically adjusted to reflect the change in latencies."

Answer 1

[Bharath Venkataraman]

You can try using the HDL reciprocal block followed by a multiply to perform this operation.

[kim lee]

Hi!

Could you let me know more how to use HDL reciprocal block in "HDLCODER"?

For example,

If I want to do the below division, what am I supposed to do in hdlcoder?

dstY = 4096;

for y = 1:255 
  v = y / (dstY);
end

I can't find any HDL Reciprocal options in HDLCODER.

[Bharath Venkataraman]

This is a Simulink block. If you drag the block into a Simulink model, and feed it dstY, it will return (1/dstY) at the output.