In the AUTOSAR sense for the RTE, the main difference is the following:
- ImplicitReceive: The input is always buffered. So, the input value remains the same in a single execution of the runnable, no matter how many times it is used.
- ExplicitReceive: The input is not buffered. So, the input value changes whenever it is used within a single execution of the runnable.
However, when generating code from Simulink, the code for the explicit case can be seen as buffered in the code, as shown in the examples below:
1) ImplicitReceive
/* Model step function for TID1 */
void Runnable_2s(void) /* Sample time: [2.0s, 0.0s] */
{
/* Update for RateTransition: '<Root>/RateTransition' incorporates:
* DiscreteIntegrator: '<Root>/Integrator'
*/
Rte_IrvIWrite_Runnable_2s_IRV1(rtDW.Integrator_DSTATE);
/* Update for DiscreteIntegrator: '<Root>/Integrator' incorporates:
* Inport: '<Root>/In2_2s'
*/
rtDW.Integrator_DSTATE += 2.0 * Rte_IRead_Runnable_2s_ReceivePort_In2();
}
2) ExplicitReceive
/* Model step function for TID1 */
void Runnable_2s(void) /* Sample time: [2.0s, 0.0s] */
{
real_T tmpRead;
/* Inport: '<Root>/In2_2s' */
Rte_Read_ReceivePort_In2(&tmpRead);
/* Update for RateTransition: '<Root>/RateTransition' incorporates:
* DiscreteIntegrator: '<Root>/Integrator'
*/
Rte_IrvIWrite_Runnable_2s_IRV1(rtDW.Integrator_DSTATE);
/* Update for DiscreteIntegrator: '<Root>/Integrator' */
rtDW.Integrator_DSTATE += 2.0 * tmpRead;
}
As it can be observed from the code above, the explicit case can be considered buffered in the sense that "tmpRead" is used in the algorithm instead of direct calls to "Rte_Read".
This is required in order to make code and simulation behaviors match, because, in Simulink, a signal is always buffered, and there is no notion of a signal line changing value in the middle of a time step between downstream blocks reading it.
