I am designing a 3rd order delta sigma ADC in simulink. I use a single bit quantiser for the design since it just replicates a comparator in the actual design.
For a single bit quantizer I could use the sign block in the Simulink. But I see that single bit quantizer (B=1, ie number of levels =2) has issues such as overloading of the quantizer and instablity for higher orders. Because of this the Dynamic range is also lower.
Now, I would like to make simulations for different quantization levels other than 2, such as B=2,3,4 and 5 bits (levels 4,8,16 and 32). For this which is the optimum model from the simulink block to use? I would like a linear quantizer block.
I tried using Quantizer block, ADC Quantiser block, Scalar quantiser decoder etc. The quantizer block is fine, since I can put the quantization interval (eg: 1 for 2 levels, 0.5 for 4 levels etc..). But For higher orders I am not getting the expected results from it. When I use the ADC Quantizer block, It doesnot give different levels at the output, rather it toggles only between 2 random values (like a single bit quantiser even if I specify the number of bits to be higher than 1), though I put the Vmin=-1 and Vmax=+1, since my FS =2.
How can I modify the ADC quantizer block to behave properly for showing up multiple levels for multiple bits?
Or can I design my own quantiser block in the simulink. I could see an Scalar Quantizer Design block from the SQD tool. Should I use that to create my quantizer? I do not know how to manipulate the SQD tool boy to create a 4 level Quantizer(2 bits), to toggle between +-1, with uniform levels [-1 -0.5 0.5 1].
Please help me to find a solution