FFT Error on FPGA with FPGA in the Loop workflow

I recently started to work with FPGA's and I am currently trying to implement an FFT on the FPGA of my Zedboard.

For this purpose I started with this simple example:

https://de.mathworks.com/help/dsp/examples/generate-hdl-code-for-fft-hdl-optimized-block.html

My main aim would be to use IP Core Generation Workflow, however, therefore no complex values are supported yet (if somebody knows how to solve this problem tell me pls!).

So, instead of IP Core Generation I am trying to use the "FPGA in the Loop" Workflow. Unfortunetaly the results when I try to do the FFT on the FPGA diverges massively from when I just do it with the HDL Coder Block in Simulink (see in the Pictures, on the left the FFT on the FPGA).

Obviously it is indeed the same signal but somehow it looks like a quantisation Error or something to me.

The FIL-model is also attached to the question.

So my question is, if somebody got an idea through which causes this kind of error can arise.

Thanks in advance!

[Navya Seelam]

Why did you use Complex to Real-Imag block when the Out1 is always real?

Answer 1

[zhang zheng]

i've tested the simulink model you attached. i think maybe you attached the wrong model?

in the attached model,

1. you combine the real and imag part togeter as an uint32 as the input to the fft. i think no need to do this. you can just input the data as complex data, and fixdt(1,16,13).

2. the dimension of the data source is 8, i think this may lead 8 fft processors in parallel. you can try scalar input first.