Azzera filtri
Azzera filtri

Build ramp in Simulink for DSP implementation

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Marzieh Karami
Marzieh Karami il 17 Dic 2019
Commentato: Jag il 9 Dic 2020
I am using a counter limited block to make the angle signal for PWM generation. I use fixed point 32 bit signals, When I run the simulation in simulink the signal frequency is 60 Hz but when I run the DSP the signal output is 50 Hz. Do you know what I am missing here?
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Jag
Jag il 9 Dic 2020
Hi Marzieh,
What is the number of bits by which you shift the signal coming into the Shift Arithmetic block?
Thanks!
Jag

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