While HLS does take C/C++ as an input, it typically requires some amount of hardware specification to successfully generate HDL. MATLAB Coder and Simulink Coder produce code intended for C/C++ compilers. So the code contains constructs that C/C++ compilers know how to implement in software but is too ambiguous for an HLS tool to automatically implement in fixed-resource hardware. Examples include unbounded loops, dynamically-sized arrays, dynamic memory allocation, pointers, and recursion.
Even in simpler cases where the generated C/C++ can run through HLS, it can be challenging for an HLS tool to generate efficient hardware without some amount of hardware specification. For instance whether a loop is completely unrolled into parallel hardware threads vs not unrolled to conserve hardware resources, or some balance of the two. Other examples include FIR filter architectures, complex multiplication implementations in FFTs, insertion of registers to break up long timing paths, and optimizing fixed-point data types for efficient resource usage.
Most HLS tools support SystemC® (IEEE Std. 1666™-2011) for adding these hardware constructs to C code in so you can simulate this functionality before running it through HLS. Some HLS tools let you describe hardware implementations as non-executable compiler directives, or “pragmas”, which results in this new functionality being added during HLS so simulation results often differ between pre- and post-HLS. But manually editing C/C++ generated from Simulink or MATLAB introduces manual coding error risks and guarantees that the functionality will differ from what you simulated in MATLAB or Simulink.
This is why for algorithms developed using MATLAB and Simulink, the most deterministic path to closure is to adapt them for streaming behavior, add hardware architecture, and quantize to fixed-point directly in MATLAB and Simulink, and generate HDL directly from this verified implementation model using HDL Coder. This allows algorithm and hardware engineers to collaborate to make high-level tradeoffs while incrementally adding implementation refinements and verifying each step, followed by HDL code generation that will match this verified behavior.