SIMULINK model simulation with variable and fixed step size

Hello,

I have a model that has an internal 0.5s delay that I need to check in my simulation. The delay is done by a block which takes an input signal and delays it by desired time. The input signal is binary (boolean) and has rising and falling edges. The delay block is configured such that it will delay the signal by rising/falling edge, but not both. For example, some delay blocks will only delay the input signal if it has rising-edge sensitivity, and some will do for falling-edgees.

When I do unit testing on my model, my solver is in fixed step and ODE5 (Dormand Prince). My step size is set to auto.

When I try to evaluate whether or not the delay is being enforced correctly, I try to calculate the delay by counting how many output samples does it take to change 0 to 1. Then I multiply it by the currentSampleTime which can be obtained by probing my input signal. All my input signal has got sample time as -1 i.e. inherited.

In this way, I get correct results as long as my simulation time is >= 5s. However, When I got beyond that, it doesn't give me a correct delay value. The actual value comes out to be 0.588 or 0.6 or 0.39 etc. The simulation output vector size comes to 51 x 1.

However, when I change the step size from AUTO to 1e-2. The number of output elements in my simulation output changes. It grows bigger as I increase my simulation time from 5 to 10 seconds and so on.

What I am trying to understand is that how AUTO step size and enforced step sizes affect simuluation. Does SIMULINK restricts the total number of data points when I set solver to Fixed Step but do not define any step size? Is that why the total number of output data points was the same regardless of my simulation time?