ASIC Testbench for HDL Verifier

Generate testbenches for ASIC and advanced FPGA designs

ASIC Testbench for HDL Verifier™ is an add-on that enables HDL Verifier to generate testbench components from MATLAB® or Simulink® into Universal Verification Methodology (UVM) or SystemVerilog environments . (MATLAB Coder™, Simulink Coder™, or Embedded Coder® is required for UVM and SystemVerilog generation.)

The ASIC Testbench add-on enables HDL Verifier to generate SystemVerilog Direct Programming Interface (DPI) components from functions or models. You can then use the component as a behavioral model in your HDL simulation environment. These components can serve different roles in the testbench such as tests, stimulus/ expected results generation, scoreboards, drivers, or monitors.

HDL Verifier can generate UVM test environments in the form of native UVM code when enabled by the ASIC Testbench add-on. UVM environments can includes a UVM top module, with a behavioral design under test (DUT) and a UVM testbench. You can replace the DUT with your own HDL DUT or take portions of the testbench and use them in your UVM test environment.

In addition, the ASIC Testbench add-on enables HDL Verifier to export SystemC™ TLM-compatible transaction-level models. You can integrate this component into your HDL simulation as a behavioral model. HDL Verifier generates a TLM testbench, test vectors, and a makefile to verify the component and assist with integration into your HDL simulator environment. (Simulink Coder or Embedded Coder® is required for SystemC TLM generation.)

HDL Verifier can generate assertions and functional coverage points for Simulink models, instrument designs with debug testpoints, allow custom SystemVerilog and UVM wrappers for MATLAB functions, and generate compilation and simulation scripts for simulators from Cadence®, Synopsys®, Siemens® and AMD® Xilinx®.