HDL Coder Evaluation Reference Guide

Getting started guide for learning and evaluating HDL Coder
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Updated 31 Dec 2023

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HDL-Coder-Evaluation-Reference-Guide

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Guidelines for getting started using HDL Coder to generate VHDL or Verilog to target FPGA or ASIC hardware. The document provides practical guidance for:

  • Setting up your MATLAB algorithm or Simulink model for HDL code generation
  • How to create HDL-ready Simulink models, Stateflow charts, and MATLAB Function blocks
  • Tips and advanced techniques for HDL code generation
  • Code generation settings for specific FPGA/SoC targets, including AXI interfaces
  • Converting to fixed-point or utilizing native floating-point
  • Optimizing for various goals and targets
  • Verifying your generated code

Examples are included to illustrate selected concepts.

Cite As

MathWorks HDL Coder Team (2024). HDL Coder Evaluation Reference Guide (https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v4.0.0), GitHub. Retrieved .

MATLAB Release Compatibility
Created with R2023a
Compatible with R2023a to R2023b
Platform Compatibility
Windows macOS Linux

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Version Published Release Notes
4.0.0

See release notes for this release on GitHub: https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v4.0.0

3.0.0

See release notes for this release on GitHub: https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v3.0.0

2.4.0.0

Updated for R2018b

2.3.0.0

Japanese translation of R2017b update

2.2.0.0

Updated to R2017b

2.1.0.0

Updated Japanese version for R2016b

2.0.0.0

Updated for R2016b

1.1.0.0

Added Japanese version of the guide

1.0.0.0

To view or report issues in this GitHub add-on, visit the GitHub Repository.
To view or report issues in this GitHub add-on, visit the GitHub Repository.