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HDL Coder Evaluation Reference Guide

version 3.0.0 (3.02 MB) by Jack Erickson
Getting started guide for learning and evaluating HDL Coder


Updated 06 Nov 2020

From GitHub

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Editor's Note: This file was selected as MATLAB Central Pick of the Week

Guidelines for getting started using HDL Coder to generate VHDL or Verilog to target FPGA or ASIC hardware. The document provides practical guidance for:

* Setting up your MATLAB algorithm or Simulink model for HDL code generation
* How to create HDL-ready Simulink models, Stateflow charts, and MATLAB Function blocks
* Tips and advanced techniques for HDL code generation
* Code generation settings for specific FPGA/SoC targets, including AXI interfaces
* Converting to fixed-point or utilizing native floating point
* Optimizing for various goals and targets
* Verifying your generated code

It also includes examples to illustrate selected concepts.

Cite As

Jack Erickson (2021). HDL Coder Evaluation Reference Guide (, GitHub. Retrieved .

Comments and Ratings (28)

ping lu

Eric Cigan

Jinyu Zhang

Jose Caballero

Jing Ma

Sercan Egilmezkol

Pablo Romero

Werner Bachhuber

yongcun liu


Akio Murakami

Tohru Kikawada

Sam Jeong

Pierre Nowodzienski

Ryan Hawl

Stephan van Beek

Damon Van Buren

yang li

Steve Kuznicki


Pierre Nowodzienski

Tom Richter

Pierre Nowodzienski

Robert Anderson

Excellent articulation on guidelines for getting the optimal performance for a wide variety of modeling constructs!

Sam Jeong

I think this reference guide would be very useful to our customer. Thanks for your efforts!

Atsushi Matsumoto


Tohru Kikawada

Eric Cigan


MATLAB Release Compatibility
Created with R2020b
Compatible with any release
Platform Compatibility
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