Community Profile

photo

Poorren


Last seen: 14 giorni fa |  Attivo dal 2017

Followers: 0   Following: 0

Contatto

Statistiche

  • Thankful Level 1
  • First Review

Visualizza badge

Feeds

Visto da

Domanda


How to disable clockdriver logic and clr port (automatic added) in generated vhdl code?
The dev enviroment of my experiment is Matlab 2020b with Vivavdo 2020. I attached the sysgen model and relative configuration f...

7 mesi fa | 1 risposta | 0

1

risposta

Domanda


tristate input in hdl verifier?
Hi guys, I met a problem on how to generate tristate bus stimulus in hdl verifier. In details, I need to verify a bus read/writ...

oltre un anno fa | 0 risposte | 0

0

risposte

Domanda


How to update HDL verifier block when VHDL source changes its port definition?
I couldn't find a way to update the block when vhdl source change its source file. So, I have to manually add or remove those de...

oltre un anno fa | 2 risposte | 0

2

risposte

Domanda


Exception on debug C shared library based application when using visual studio 2017
Hello guys, Now, I try and study to use Matlab library compiler to convert matlab script to library function, and call it in C ...

oltre un anno fa | 1 risposta | 0

1

risposta

Domanda


Question on zp2sos gain scaling?
Hello guys, I have a question on matlab zp2sos function. The question is how matlab do scaling when convert z/p/k to zeros...

oltre 6 anni fa | 0 risposte | 0

0

risposte