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Yeung Pok Nga


Last seen: 4 mesi fa |  Attivo dal 2023

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Domanda


Relationship between FPGA Sample Frequency, FPGA Clock Frequency, Simulink Solver Rate and Oversampling Factor
Hi, I have a generator controller model in Simulink, I'm hoping to have it deployed on Speedgoat (IO334-325k) and use it to run ...

5 mesi fa | 1 risposta | 0

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Domanda


HDL Coder Vivado timing report shows infinite slack
I'm using HDL coder to deploy a controller model in simulink onto Speedgoat FPGA, at the build bitstream stage i get a message s...

7 mesi fa | 1 risposta | 0

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Domanda


HDL Coder timing report shows a different negative slack when building the exact model twice
I'm using HDL coder to deploy a controller model i have onto Speedgoat FPGA. I'm using Vivado as the compiler and the fpga manuf...

7 mesi fa | 1 risposta | 0

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Domanda


HDL Coder, Assertion failed: B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()
I have a HDL Coder Simulink Model in R2021a. The model consists of a generator and a controller. I'm trying to convert the contr...

oltre un anno fa | 1 risposta | 0

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