Statistica
RANK
299.929
of 300.771
REPUTAZIONE
0
CONTRIBUTI
2 Domande
1 Risposta
ACCETTAZIONE DELLE RISPOSTE
0.0%
VOTI RICEVUTI
0
RANK
of 170.969
CONTRIBUTI
0 Problemi
0 Soluzioni
PUNTEGGIO
0
NUMERO DI BADGE
0
CONTRIBUTI
0 Post
CONTRIBUTI
0 Pubblico Canali
VALUTAZIONE MEDIA
CONTRIBUTI
0 Punti principali
NUMERO MEDIO DI LIKE
Feeds
Domanda
Referenced model output of three phase voltage and current are 65535
I had converted the matlab function block into referenced model for running in Processor-In-Loop (PIL) and I had kept the code i...
13 giorni fa | 1 risposta | 0
1
rispostaRisposto
Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32""
In HDL coder setting enable Scalarize ports. Steps for enabling Scalarize ports: HDL code --> Setting --> Configuration parame...
Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32""
In HDL coder setting enable Scalarize ports. Steps for enabling Scalarize ports: HDL code --> Setting --> Configuration parame...
circa un mese fa | 0
Domanda
sampling time mismatch in simulink and harware
i am having a simulink model in matlab which is running on sampling time of 5e-6 second now i want to run my matlab file in zedb...
circa un mese fa | 2 risposte | 0
