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Wrap Xilinx IP in Simulink black box
https://www.mathworks.com/help/hdlcoder/examples/using-xilinx-system-generator-for-dsp-with-hdl-coder.html Using the Xilinx Sys...

circa 6 anni fa | 0

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HDL Coder. Undefined function or variable '***'. The first assignment to a local variable determines its class.
Hi Salvador, Can you share a testbench file for this design? Test bench determines the compute the input types used to compile t...

circa 6 anni fa | 0

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Can't Get Rid of UseMatrixTypesInHDL Warning
This is not exepcted behavior. Please reach out to support@mathworks.com for additional help. In 20b pre-release this option is...

circa 6 anni fa | 0

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Complex to Magnitude-Angle HDL Optimized does not get converted to clock-rate
The "Complex to Magnitude-Angle HDL Optimized" simulates latency in the original model and does not participate in clock rate pi...

oltre 6 anni fa | 1

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Failed to program the device of the Zedboard Using matlab R2019b
Hi Yuhwai, This is unexpected. Please report the issue to support@mathworks.com for further support.

oltre 6 anni fa | 0

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Error "Brace indexing ist not supported for variables of this type" in HDL Workflow Advisor
Hi Niklas, This is unexpected. Please report the issue to support@mathworks.com for further support.

oltre 6 anni fa | 0

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How to optimize multiplications with hdl coder
ConstMultiplierOptimization The ConstMultiplierOptimization implementation parameter lets you specify use of canonical signed d...

oltre 6 anni fa | 1

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What is the good manner of generating the HDL Code of a mixed Simscape/Simulink model ?
Simscape Hardware-in-the-Loop Workflow Automatic replacement of Simscape subsystem with state-space implementation In R2020b, ...

oltre 6 anni fa | 1

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Internal Error in generation of HDL IP core for a Xilinx platform
Can you explain why you would need to force the subsystem to be atomic for Zynq targeting? I totally understand the additional ...

oltre 6 anni fa | 0

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Internal Error in generation of HDL IP core for a Xilinx platform
Firstly, you need to fix algebraic loop option on the FPGA DUT by turning off this option as follows set_param('PID_example2...

oltre 6 anni fa | 0

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How can i generate testbench data for fixed point range
Hi, for better guidance, can you share your sample model that you plan to take to HDL code generation? Thanks.

oltre 6 anni fa | 0

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How to connect bus data type to external port interface?
Bus support for External Port is not yet supported in HDLCoder and is under active development and will be available in the near...

oltre 6 anni fa | 0

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Why it occur overflow??
The overflow behavior is based on what kinds of operations are happening on the variable. Is it in a feedback look like a for-lo...

oltre 6 anni fa | 1

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CWT Filter Bank Function
Generating code FPGA cannot support variable dimensions as HDLCoder needs to generate code for a chip with fixed size, type, dim...

oltre 6 anni fa | 0

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Is there a way to change the parameter in simulink??
Have you considered using to workspace and from workspace blocks and logging your time series data and reading it back in?

oltre 6 anni fa | 0

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Is there a 'block' similar to MATLAB's 'persistent' in simulink??
I am not using any new Simulink features; so you can try to load the model in your version. Try this to load the model. >> s...

oltre 6 anni fa | 1

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Is there a 'block' similar to MATLAB's 'persistent' in simulink??
Attached model shows how to model unit delay, integer delay, tapped delay in MALTAB and corresponding blocks/modeling patterns i...

oltre 6 anni fa | 0

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HDL Workflow Advisor error
Hi, This is an unexpected internal error. Can you share the model?

oltre 6 anni fa | 0

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HDL Coder returns with error "Unrecognized fixed-point encoding"
can you reach out to support@mathworks.com to help debug this error further? thanks

oltre 6 anni fa | 0

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Codegen parfor + singleC
parfor support is an active area of development for -singleC feature; please feel free to reach out to us support@mathworks.co...

oltre 6 anni fa | 0

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Cell arrays are not supported when using the -singleC flag (Coder)
cell array support is an active area of development for -singleC feature; please feel free to reach out to us support@mathwork...

oltre 6 anni fa | 0

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Matlab Options for Programming Labview R-series FPGA card.
Please let us know if this tutorial is somethign that can be used in your case. MATLAB®, Simulink®, and LabVIEW FPGA: Importing...

oltre 6 anni fa | 0

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HDL Coder returns with error "Unrecognized fixed-point encoding"
Hi Tim, Based on the error message this does not seem to be coming during code generation process. Are you sure you able to com...

oltre 6 anni fa | 0

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HDL code generation from simulink and dumping process
The question is a bit vague; can you provide more specifcis on your workflow issues? HDLCoder should support cyclone V workflo...

oltre 6 anni fa | 0

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how to use exp funnction in hdl coder?
Hi, Can you add more details and share example files with projects and reproductions here so that we can give better guidance?...

oltre 6 anni fa | 0

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Implementation Latency of Blackbox Subsystem when using oversampling
We are also able to generate code for the mockup model.

oltre 6 anni fa | 0

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Implementation Latency of Blackbox Subsystem when using oversampling
With HDLCoder we have done a very detailed Fied-Oriented Controller model on FPGA/SoC. See the attached document. Happy to...

oltre 6 anni fa | 0

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Matlab coder, fixed point conversion
Hi Jerome, Can you share a sample of MATLAB code with floating-point and expected integer type code from fixed-point converter?...

oltre 6 anni fa | 0

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Can't open HDL Workflow Advisor
Glad the solution helped. It is quite possible the device you are planning to use is not supported in 19a. You can check this...

oltre 6 anni fa | 0

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Can't open HDL Workflow Advisor
Please try this and if this does not help it is best to have a clean install. >>Advisor.Manager.refresh_customizations Or >>r...

oltre 6 anni fa | 0

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