Manipulate Delays

Delays and Alignment Problems

Some models require you not only to compute delays but to manipulate them. For example, if a model incurs a delay between a block encoder and its corresponding decoder, the decoder might misinterpret the boundaries between the codewords that it receives and, consequently, return meaningless results. More generally, such a situation can arise when the path between paired components of a block-oriented operation (such as interleaving, block coding, or bit-to-integer conversions) includes a delay-causing operation (such as those listed in Causes of Processing Delay).

To avoid this problem, you can insert an additional delay of an appropriate amount between the encoder and decoder. If the model also computes an error rate, then the additional delay affects that process. This section uses examples to illustrate the purpose, methods, and implications of manipulating delays in a variety of circumstances.

This section illustrates the sensitivity of block-oriented operations to delays, using a small model that aims to capture the essence of the problem in a simple form. Then run the simulation so that the Display blocks show relevant values.

In this model, two coding blocks create and decode a block code. Two copies of the Delay block create a delay between the encoder and decoder. The two Delay blocks have different purposes in this illustrative model:

The Inherent Delay block represents any delay-causing blocks that might occur in a model between the encoder and decoder.
The Added Delay block is an explicit delay that you insert to produce an appropriate amount of total delay between the encoder and decoder.

Observing the Problem

By default, the Delay parameters in the Inherent Delay and Added Delay blocks are set to 1 and 0, respectively. This represents the situation in which some operation causes a one-bit delay between the encoder and decoder, but you have not yet tried to compensate for it. The total delay between the encoder and decoder is one bit. You can see from the blocks labeled Word and Delayed Word that the codeword that leaves the encoder is shifted downward by one bit by the time it enters the decoder. The decoder receives a signal in which the boundary of the codeword is at the second bit in the frame, instead of coinciding with the beginning of the frame. That is, the codewords and the frames that hold them are not aligned with each other.

This nonalignment is problematic because the Hamming Decoder block assumes that each frame begins a new codeword. As a result, it tries to decode a word that consists of the last bit of one output frame from the encoder followed by the first six bits of the next output frame from the encoder. You can see from the Error Rate Display block that the error rate from this decoding operation is close to 1/2. That is, the decoder rarely recovers the original message correctly.

To use an analogy, suppose someone corrupts a paragraph of prose by moving each period symbol from the end of the sentence to the end of the first word of the next sentence. If you try to read such a paragraph while assuming that a new sentence begins after a period, you misunderstand the start and end of each sentence. As a result, you might fail to understand the meaning of the paragraph.

To see how delays of different amounts affect the decoder's performance, vary the values of the Delay parameter in the Added Delay block and the Receive delay parameter in the Error Rate Calculation block and then run the simulation again. Many combinations of parameter values produce error rates that are close to 1/2. Furthermore, if you examine the transmitted and received data by entering

[tx rx]

at the MATLAB command line, you might not detect any correlation between the transmitted and received data.

Correcting the Delays

Some combinations of parameter values produce error rates of zero because the delays are appropriate for the system. For example:

In the Added Delay block, set Delay to 6.
In the Error Rate Calculation block, set Receive delay to 4.
Run the simulation.
Enter [tx rx] at the MATLAB command line.

The top number in the Error Rate Display block shows that the error rate is zero. The decoder recovered each transmitted message correctly. However, the Word and Displayed Word blocks do not show matching values. It is not immediately clear how the encoder's output and the decoder's input are related to each other. To clarify the matter, examine the output in the MATLAB command window. The sequence along the first column (tx) appears in the second column (rx) four rows later. To confirm this, enter

isequal(tx(1:end-4),rx(5:end))

at the MATLAB command line and observe that the result is 1 (true). This last command tests whether the first column matches a shifted version of the second column. Shifting the MATLAB vector rx by four rows corresponds to the Error Rate Calculation block's behavior when its Receive delay parameter is set to 4.

To summarize, these special values of the Delay and Receive delay parameters work for these reasons:

Combined, the Inherent Delay and Added Delay blocks delay the encoded signal by a full codeword rather than by a partial codeword. Thus the decoder is correct in its assumption that a codeword boundary falls at the beginning of an input frame and decodes the words correctly. However, the delay in the encoded signal causes each recovered message to appear one word later, that is, four bits later.
The Error Rate Calculation block compensates for the one-word delay in the system by comparing each word of the transmitted signal with the data four bits later in the received signal. In this way, it correctly concludes that the decoder's error rate is zero.
Note
These are not the only parameter values that produce error rates of zero. Because the code in this model is a (7, 4) block code and the inherent delay value is 1, you can set the Delay and Receive delay parameters to 7k-1 and 4k, respectively, for any positive integer k. It is important that the sum of the inherent delay (1) and the added delay (7k-1) is a multiple of the codeword length (7).

Aligning Words of a Block Code

An ADSL illustrates the need to manipulate the delay in a model so that each frame of data that enters a block decoder has a codeword boundary at the beginning of the frame. The need arises because the path between a block encoder and block decoder includes a delay-causing convolutional interleaving operation. This section explains why the model uses a Delay block to manipulate the delay between the convolutional deinterleaver and the block decoder, and why the Delay block is configured as it is.

Misalignment of Codewords

In the ADSL example, the Convolutional Interleaver and Convolutional Deinterleaver blocks appear after the Scrambler & FEC subsystems but before the Descrambler & FEC subsystems. These two subsystems contain blocks that perform Reed-Solomon coding, and the coding blocks expect each frame of input data to start on a new word rather than in the middle of a word.

The delay of the interleaver and deinterleaver pair is 40 samples. However, the input to the Descrambler & FEC subsystem is a frame of size 840, and 40 is not a multiple of 840. Consequently, the signal that exits the Convolutional Deinterleaver block is a frame whose first entry does not represent the beginning of a new codeword. As described in Observing the Problem, this misalignment, between codewords and the frames that contain them, prevents the decoder from decoding correctly.

Inserting a Delay to Correct the Alignment

The ADSL example solves the problem by moving the word boundary from the 41st sample of the 840-sample frame to the first sample of a successive frame. Moving the word boundary is equivalent to delaying the signal. To this end, the example contains a Delay block between the Convolutional Deinterleaver block and the Descrambler & FEC subsystem.

The Delay parameter in the Delay block is 800 because that is the minimum number of samples required to shift the 41st sample of one 840-sample frame to the first sample of the next 840-sample frame. In other words, the sum of the inherent 40-sample delay (from the interleaving/deinterleaving process) and the artificial 800-sample delay is a full frame of data, not a partial frame.

This 800-sample delay has implications for other parts of the model, specifically, the Receive delay parameter in one of the Error Rate Calculation blocks. For details about how the delay influences the value of that parameter.

Using the Find Delay Block

The preceding discussion explained why an 800-sample delay is necessary to correct the misalignment between codewords and the frames that contain them. Knowing that the Descrambler & FEC subsystem requires frame boundaries to occur on word boundaries, you could have arrived at the number 800 independently by using the Find Delay block. Use this procedure:

Insert a Find Delay block and a Display block in the model.
Create a branch line that connects the input of the Convolutional Interleaver block to the sRef input of the Find Delay block.
Create another branch line that connects the output of the Convolutional Deinterleaver block to the sDel input of the Find Delay block.
Connect the delay output of the Find Delay block to the new Display block. The modified part of the model now looks like the following image (which also shows drop shadows on key blocks to emphasize the modifications).
Show the dimensions of each signal in the model. On the Debug tab, expand Information Overlays. In the Signals section, select Signal Dimensions.
Run the simulation.

The new Display block now shows the value 40. Also, the display of signal dimensions shows that the output from the Convolutional Deinterleaver block is a frame of length 840. These results indicate that the sequence of blocks between the Convolutional Interleaver and Convolutional Deinterleaver, inclusive, delays an 840-sample frame by 40 samples. An additional delay of 800 samples brings the total delay to 840. Because the total delay is now a multiple of the frame length, the delayed deinterleaved data can be decoded.

Aligning Words for Interleaving

This section describes an example that manipulates the delay before a deinterleaver, because the path between the interleaver and deinterleaver includes a delay from demodulation.

The model includes block coding, helical interleaving, and GMSK modulation. The table below summarizes the individual block delays in the model.

Block	Delay, in Output Samples from Individual Block	Reference
GMSK Demodulator Baseband	16	Delays in Digital Demodulation
Helical Deinterleaver	42	Delays of Convolutional Interleavers
Delay	5	Delay reference page

Misalignment of Interleaved Words

The demodulation process in this model causes a delay between the interleaver and deinterleaver. Because the deinterleaver expects each frame of input data to start on a new word, it is important to ensure that the total delay between the interleaver and deinterleaver includes one or more full frames but no partial frames.

The delay of the demodulator is 16 output samples. However, the input to the Helical Deinterleaver block is a frame of size 21, and 16 is not a multiple of 21. Consequently, the signal that exits the GMSK Demodulator Baseband block is a frame whose first entry does not represent the beginning of a new word. As described in Observing the Problem, this misalignment between words and the frames that contain them hinders the deinterleaver.

Inserting a Delay to Correct the Alignment

The model moves the word boundary from the 17th sample of the 21-sample frame to the first sample of the next frame. Moving the word boundary is equivalent to delaying the signal by five samples. The Delay block between the GMSK Demodulator Baseband block and the Helical Deinterleaver block accomplishes such a delay. The Delay block has its Delay parameter set to 5.

Combining the effects of the demodulator and the Delay block, the total delay between the interleaver and deinterleaver is a full 21-sample frame of data, not a partial frame.

Checking Alignment of Block Codewords

The interleaver and deinterleaver cause a combined delay of 42 samples measured at the output from the Helical Deinterleaver block. Because the delayed output from the deinterleaver goes next to a Reed-Solomon decoder, and because the decoder expects each frame of input data to start on a new word, it is important to ensure that the total delay between the encoder and decoder includes one or more full frames but no partial frames.

In this case, the 42-sample delay is exactly two frames. Therefore, it is not necessary to insert a Delay block between the Helical Deinterleaver block and the Binary-Output RS Decoder block.

Computing Delays to Configure the Error Rate Calculation Blocks

The model contains two Error Rate Calculation blocks, labeled Channel Error Rate and System Error Rate. Each of these blocks has a Receive delay parameter that must reflect the delay of the path between the block's Tx and Rx signals. The following table explains the Receive delay values in the two blocks.

Block	Receive Delay Value	Reason
Channel Error Rate	`16`	Delay of GMSK Demodulator Baseband block, in samples
System Error Rate	`15*3`	Three fifteen-sample frames: one frame from the GMSK Demodulator Baseband and Delay blocks, and two frames from the interleaver and deinterleaver pair

Aligning Words of a Concatenated Code

This section describes an example that manipulates the delay between the two portions of a concatenated code decoder, because the first portion includes a delay from Viterbi decoding while the second portion expects frame boundaries to coincide with word boundaries. It uses the block and convolutional codes from the Digital Video Broadcasting - Terrestrial example, but simplifies the overall design a great deal.

The model includes a shortened block code and a punctured convolutional code. All signals and blocks in the model share the same frame period. The following table summarizes the individual block delays in the model.

Block	Delay, in Output Samples from Individual Block
Viterbi Decoder	136
Delay	1496 (that is, 1632 - 136)

Misalignment of Block Codewords

The Viterbi decoding process in this model causes a delay between the Integer to Bit Converter block and the Bit to Integer Converter block. Because the latter block expects each frame of input data to start on a new 8-bit word, it is important to ensure that the total delay between the two converter blocks includes one or more full frames but no partial frames.

The delay of the Viterbi Decoder block is 136 output samples. However, the input to the Bit to Integer Converter block is a frame of size 1632. Consequently, the signal that exits the Viterbi Decoder block is a frame whose first entry does not represent the beginning of a new word. As described in Observing the Problem, this misalignment between words and the frames that contain them hinders the converter block.

Note

The outer decoder in this model (Integer-Output RS Decoder) also expects each frame of input data to start on a new codeword. Therefore, the misalignment issue in this model affects many concatenated code designs, not just those that convert between binary-valued and integer-valued signals.

Inserting a Delay to Correct the Alignment

The model moves the word boundary from the 137th sample of the 1632-sample frame to the first sample of the next frame. Moving the word boundary is equivalent to delaying the signal by 1632-136 samples. The Delay block between the Viterbi Decoder block and the Bit to Integer Converter block accomplishes such a delay. The Delay block has its Delay parameter set to 1496.

Combining the effects of the Viterbi Decoder block and the Delay block, the total delay between the interleaver and deinterleaver is a full 1632-sample frame of data, not a partial frame.

Computing Delays to Configure the Error Rate Calculation Blocks

The model contains two Error Rate Calculation blocks, labeled Inner Error Rate and Outer Error Rate. Each of these blocks has a Receive delay parameter that must reflect the delay of the path between the block's Tx and Rx signals. The table below explains the Receive delay values in the two blocks.

Block	Receive Delay Value	Reason
Inner Error Rate	`136`	Delay of Viterbi Decoder block, in samples
Outer Error Rate	`1504 (188*8 bits)`	One 188-sample frame, from the combination of the inherent delay of the Viterbi Decoder block and the added delay of the Delay block

Aligning Words for Nonlinear Digital Demodulation

This example manipulates delay in order obtain the correct symbol synchronization of a signal so that symbol boundaries correctly align before demodulation occurs.

This model includes a CPFSK modulation scheme and pulse shaping filter. For the demodulation to work properly, the input signal to the CPFSK demodulator block must have the correct alignment. Various blocks in this model introduce processing delays. Because of these delays, the input signal to the CPFSK demodulator block is not in the correct alignment.

Both the Raised Cosine Transmit and Receive Filter blocks introduce a delay. The delay is defined as: $G r o u p D e l a y \cdot T s$

where Ts represents the input sample time of the Raised Cosine Transmit Filter block.

The input sample time of the Raised Cosine Transmit Filter block equals the output sample time of the Raised Cosine Receive Filter block. Therefore, the total delay at the output of the Raised Cosine Receive Filter is:

$2 \cdot G r o u p D e l a y \cdot T s$

or $8 \cdot T s$

as GroupDelay = 4

The CPFSK demodulator block receives this delayed signal, and then it processes each collection of 8 samples per symbol to compute 1 output symbol. You must ensure that the CPFSK demodulator receives input samples in the correct collection of samples. For binary CPFSK with a Modulation index of 1/2, the demodulator input must align along even numbers of symbols. Note that this requirement applies only to binary CPFSK with a modulation index of 1/2. Other CPM schemes with different M-ary values and modulation indexes have different requirements.

To ensure that the CPFSK demodulator in this model receives the correct collection of input samples with the correct alignment, introduce a delay of 8 samples (in this example, $8 \cdot T s$ ). The total delay at the input of the CPFSK demodulator is $16 \cdot T s$ , which equates to two symbol delays (2.T, where T is the symbol period).

In sample-based mode, the CPFSK demodulator introduces a delay of Traceback length + 1 samples at its output. In this example, Traceback length equals 16. Therefore, the total Receiver delay in the Error rate calculation block equals 17+2 or 19. For more information, see Delays in Digital Demodulation.