Shift Left and Stretch Right for First-Time Silicon Success
How semiconductor companies can accelerate development, secure design-in, and deliver customer value across the product lifecycle
In semiconductor development, first-time silicon success is about achieving not only a technical milestone, but also a business outcome. It depends on getting the right product to market at the right time and cost, securing design-in at volume, and supporting customers effectively throughout their product lifecycle. Today, semiconductor customers expect more from their suppliers. They are simulating more and adopting virtual development approaches, and they increasingly expect component models, reference examples, virtual design tooling, and production-ready software to help them reduce risk and move faster.
A shift-left, stretch-right strategy addresses both sides of that challenge. Shifting left uses modeling and simulation to help teams achieve the milestone of getting their silicon right the first time through earlier validation and then reusing engineering assets, such as models, across the development flow. Stretching right extends those same assets to customers, helping them evaluate, integrate, and evolve products more efficiently. This approach helps customers achieve their own shift left.
“Shift left, stretch right” means pulling modeling and verification earlier into the design flow while extending model reuse to customers.
AI is further accelerating this shift-left, stretch-right strategy. By augmenting modeling and simulation workflows, AI helps engineering teams reduce manual setup, automate test generation, and converge faster on design objectives, strengthening shift-left practices. AI-driven workflows and models can also be packaged and reused as part of customer-facing deliverables, thereby extending value beyond internal development. This way, AI not only improves engineering productivity but also amplifies the reuse and customer enablement benefits that underpin a successful stretch-right approach.
In this paper, we examine how companies including NXP, Nokia, STMicroelectronics, Intel, and Infineon have applied these principles to improve verification efficiency, accelerate customer adoption, and create reusable engineering assets that deliver value across the product lifecycle.
Many semiconductor organizations still operate with fragmented workflows. Specification, architecture, implementation, and verification are often distributed across different teams and tools, making it harder to keep design intent aligned from concept through signoff. The underlying cost of that fragmentation can be high: design errors introduced during development and the impact of changing requirements during the project are common contributors to ASIC delays and respins.
According to the 2024 Siemens EDA/Wilson Research Group Functional Verification Study, only 14% of ASIC/SoC projects achieved first silicon success.
A model-based workflow helps address this fragmentation by creating a unified approach in which models are reused as architectural references, verification stimuli, and implementation sources across analog and digital design and verification activities. Rather than recreating design intent repeatedly in different languages and environments, teams can use shared technical artifacts to improve consistency and accelerate iterations. This approach reduces duplicated work and aligns teams on the same “source of truth.”
The result is more than improved engineering efficiency. It is a better and more agile way to respond to customer-driven changes. When teams can update models, rerun realistic tests, and propagate changes across downstream workflows more quickly, they are better positioned to meet evolving requirements without introducing late surprises.
Shift Left: Verify Earlier, with Greater Relevance
Shifting left is often described as verifying earlier, but the most effective implementations go further. The objective is to validate the right behaviors, against the right scenarios, with assets such as models and test cases that remain useful throughout the design cycle.
For semiconductor teams, that means measuring designs against the metrics important to customers, while using inputs drawn from realistic operating conditions rather than abstract test patterns. Those models and test cases are built once so they carry through system design, implementation, and post-silicon verification.
Customer Results: Shift Left in Practice
An example of shift left in practice comes from NXP’s automotive radar work, described in the article “Environment-in-the-Loop Verification of Automotive Radar IC Designs.” The team developed a methodology that aligns internal verification with customer-driven metrics, such as signal-to-noise ratio (SNR) and total harmonic distortion (THD). Instead of relying only on abstract low-level test patterns, NXP generated verification stimuli from realistic Euro NCAP driving scenarios and used those scenarios in early system-level validation. This approach enabled virtual field trials a year before first silicon while also supporting reuse across system, RTL, and post-silicon phases.
Block diagram of a 38–40.5 GHz radar sensor IC with four Rx channels, three Tx channels, a chirp generator PLL, and supporting control blocks.
The lesson is that shift left creates the most value when it narrows the gap between internal engineering signoff and real customer usage conditions. While early verification is useful, earlier customer-relevant verification is even more powerful: by validating earlier against realistic operating contexts, teams can reduce the risk of late-stage mismatches and focus effort on the issues that matter most commercially.
“Using DPI-C models generated from MATLAB enables us to compute functional and performance metrics at multiple interfaces in the Cadence HDL verification environment. We can decouple design implementation from verification and conduct testing at a level of abstraction more closely aligned with the metrics that interest our customers.”
Other documented examples reinforce the same principle. STMicroelectronics used Simulink® and HDL Verifier™ to reuse system-level models in chip-level verification, with the reported result that RTL verification time for designs based on Simulink was cut in half. Furthermore, because verification artifacts are reused throughout different design steps, the duplication of effort between system-level and RTL-level verification was significantly reduced.
Nokia took the same idea in a different direction, adopting Model-Based Design with Simulink across a 5G digital front-end design flow. As Nokia's Sami Repo put it, this approach brought “flexibility, visibility, and capability to react” across the entire workflow, delivering faster execution, better architectural exploration, stronger cross-team communication, and quality improvements.
Together, these examples show that shift-left success depends not only on earlier execution, but on reducing duplicated work and creating a common technical language across teams.
“[This design and verification approach] also allows engineers to have a single source of test cases for the stimuli that are run at both system- and RTL-level. As a consequence, the RTL verification time has been cut in half.”
Customer Results
Across these examples, shift left delivers the most value when earlier verification is also more customer-relevant and more reusable.
| Company | What They Did | What They Accomplished |
|---|---|---|
| NXP | Generated automotive-radar verification stimuli from realistic Euro NCAP driving scenarios and validated against customer design metrics like SNR and THD. | Ran virtual field trials a full year before first silicon, with the same assets reused across system, RTL, and post-silicon. |
| STMicroelectronics | Reused system-level Simulink models directly inside chip-level UVM verification. | Cut RTL verification time in half and eliminated duplicated effort between system- and RTL-level verification. |
| Nokia | Standardized on a common Simulink modeling platform across the 5G digital front-end design flow. | Achieved faster execution and architecture exploration, plus quality gains. |
Stretch Right: Turn Engineering Assets Into Customer Advantage
Where shifting left improves internal execution, stretching right extends the same engineering investments outward as reusable assets for customers. In practical terms, that means providing reusable assets such as component models, virtual processor platforms, configuration and design tools, production-ready software components, and reference models for key applications.
This matters because customers are also seeking to shift left their own development processes. In software-defined vehicle programs and other software-intensive systems, customers want to begin development before hardware is available, and keep improving systems after deployment. Semiconductor companies that provide better virtual assets and support infrastructure make it easier for their customers to start sooner, integrate faster, and reduce project risk.
Customer Results: Stretch Right in Practice
A recent collaboration between MathWorks and NXP in battery management systems (BMS) provides a clear example of stretch right in practice. With the introduction of a dedicated Model-Based Design Toolbox for BMS, engineers can develop, validate, and automatically deploy control algorithms from MATLAB® and Simulink directly onto NXP processors, bridging the gap between system-level design and production implementation. This approach enables deployment to target hardware, including optimized code generation, access to on-chip peripherals, and processor-in-the-loop testing. These capabilities enable customers to move efficiently from modeling and simulation to real-world testing and implementation, reusing algorithms without manual recoding and validating them across realistic operating scenarios. The result is reduced integration friction, faster time to market, and a lower barrier from concept to deployment, while enhancing the overall device ecosystem and extending the value of semiconductor platforms beyond silicon. NXP’s own leadership frames the payoff in business terms, with CTO Lars Reger citing “faster design iterations that allow engineers to identify and fix issues upfront” as well as shortened time to market for the customers building on NXP silicon.
Infineon provides another clear stretch-right proof point. The company used MATLAB and Simulink to develop, verify, and deliver a complete IBIS-AMI model for a customer on an aggressive two-week timeline. In addition to meeting a tight deadline set by their customer, they achieved faster internal ramp-up, along with the development of an in-house capability that could be reused on future programs.
“The workflow we followed with SerDes Toolbox was the fastest, shortest path to delivering an IBIS-AMI model to our customer. Plus, we now have the skills and the ability to reuse parts of the model to produce IBIS-AMI models for other designs and other customers.”
For semiconductor companies, this is more than a modeling story. It is a design-in story, because accurate customer-facing models can shorten evaluation cycles and reduce friction in technical engagement without exposing internal IP. Stretching right is not just about post-silicon support but acts as a growth lever. The better the reusable assets, the easier it is for customers to adopt the platform, scale it across programs, and stay with it longer.
Top and bottom views of an Infineon QFN-package semiconductor chip.
Customer Results
These examples show stretch right working as a growth lever, turning internal engineering assets into tools that make customers faster and stickier.
| Company | What They Did | What They Accomplished |
|---|---|---|
| NXP | Delivered a Model-Based Design Toolbox for BMS that deploys control algorithms straight from MATLAB and Simulink onto NXP processors. | Removed manual recoding and integration friction, shortening their customers’ path from concept to deployment on silicon. |
| Infineon | Reused system-level Simulink models directly inside chip-level UVM verification. | Cut RTL verification time in half and eliminated duplicated effort between system-level and RTL-level verification. |
In semiconductor development, AI creates the most value when it strengthens a shift-left, stretch-right strategy. It can help engineering teams reduce manual setup, shorten simulation cycles, and cut trial-and-error across design and verification workflows. In practice, this spans copilots that assist engineers, agentic workflows that support iterative engineering loops, machine learning models that drive emulation and optimization, and workflows that deploy AI algorithms to hardware accelerators.
Customer Results: AI as a Force Multiplier
One practical use case is AI as an autonomous engineering workflow. Intel describes a multi-agent AI workflow that runs a complete signal integrity sign-off for post-layout PCIe interconnects. The design is deliberately agent-centric: a taskmaster agent interprets the goal and orchestrates specialized worker agents for extraction, compliance, and reporting, executing an approved engineering flow as a deterministic state machine so the results are reproducible rather than improvised. The engineer’s role shifts from running solvers and compiling reports to defining objectives, constraints, and success metrics and validating the output, which is exactly what a shift-left, stretch-right strategy asks AI to do.
“The engineer’s role shifts from execution to goal-setting and validation.”
Another use case is AI for verification efficiency. Nokia used MATLAB to develop a machine learning approach that reduced the number of tests needed for coverage closure by up to 2x, while improving verification quality by reducing redundant test cases. This is a strong shift-left example because AI helped the team reach coverage goals with fewer tests and less redundant simulation effort.
A third use case is AI implemented as part of the final product. NXP trained a neural network in MATLAB to post-correct ADC errors, then generated and verified the corresponding HDL implementation. When implemented on an ASIC, the network required 15% of the area of the ADC and consumed roughly 16 times less power under normal operating conditions. This example shows AI contributing directly to hardware architecture, not just engineering productivity.
Customer Results
These examples show AI strengthening the shift-left, stretch-right strategy, from verification efficiency to reproducible sign-off to silicon that carries AI on-chip.
| Company | What They Did | What They Accomplished |
|---|---|---|
| Intel | Built a multi-agent AI workflow that runs full signal integrity sign-off for post-layout PCIe interconnects. | Made sign-off reproducible and shifted the engineer’s role from running solvers to setting objectives and validating results. |
| Nokia | Applied a machine-learning approach to select 5G algorithm tests. | Reached coverage closure with up to 2x fewer tests and less redundant simulation. |
| NXP | Trained a neural network in MATLAB to post-correct ADC errors, then generated and verified the HDL for silicon. | Corrected ADC errors using just 15% of the ADC’s area and roughly 16x less power. |
Conclusion: How Semiconductor Teams Can Start
A practical starting point is to view shift left and stretch right not as isolated initiatives, but as a strategic evolution of the engineering operating model. Leadership teams should identify where earlier verification can materially reduce risk or accelerate development, while also assessing which models, workflows, and engineering assets can be extended to create customer value beyond internal development. The highest-impact opportunities are typically those that connect engineering outcomes with business results: reducing late-stage risk, accelerating customer evaluation, shortening design-in cycles, and simplifying product support and evolution. The key questions are straightforward: Which risks can be addressed earlier? Which internal assets can become scalable customer-enablement capabilities? And which pilot workflows can demonstrate measurable business value and build momentum for broader adoption?
Securing first-time silicon success depends on two connected capabilities, improving internal engineering outcomes earlier and improving customer outcomes later and longer. Shifting left strengthens architectural confidence, speeds iteration, and makes verification more relevant. Stretching right converts the same engineering assets into customer-facing tools that accelerate design-in and reduce lifecycle friction.
For semiconductor organizations facing growing complexity and tighter schedules, this is a practical and scalable strategy. Earlier modeling, realistic validation, reusable verification assets, customer-ready simulation models, and supported target workflows all contribute to a stronger competitive position. The companies that do this will not only improve their silicon development, but also improve the entire customer experience of building products around that silicon.
