You can generate HDL code for Simulink® models from the UI by using the HDL Code tab in the Simulink toolstrip or by using the Configuration Parameters dialog box. In this dialog box, you can specify various HDL code generation settings including basic folder and language selection to more advanced optimization parameters. To learn about how to generate HDL code from the HDL Code tab, see Generate HDL Code from Simulink Model.
To deploy the generated code to a target device, use the Simulink HDL Workflow Advisor. The Advisor can run end-to-end workflows that check HDL compatibility and deploy the generated code to a target device.
|Global Settings Overview|
|Language-Specific Identifiers and Postfix Parameters|
|Language-Specific File Extension Parameters|
|Comment in header|
|RTL Style Parameters|
|VHDL Architecture and Library Name and Code for Model Reference Parameters|
|File Comment Customization Parameters|
|Generate Statement and Vector and Component Instance Label Parameters|
Learn about the HDL Workflow Advisor and various workflows you can choose and platforms you can target.
Learn the basics of the HDL Workflow Advisor and how to run various tasks.
Describes HDL Workflow Advisor tasks.
The HDL Workflow Advisor guides you through the stages of generating HDL code for a Simulink subsystem and the FPGA design process, such as:
Access HDL options in the Configuration Parameters dialog box and Model Explorer; Simulink Toolstrip, HDL Code context menu, and pointers to related information.
Access HDL options under various panes in the HDL Code Generation pane of the Model Configuration Parameters dialog box.
Use the Configuration Parameters dialog box to generate HDL code for your Simulink model.
Learn how to obfuscate the generated VHDL® or Verilog® code from your model.