RAM and ROM Blocks

Mimic RAMs and ROMs on hardware using blocks in HDL RAMs library

The HDL Coder block library contains many blocks that you can add to your Simulink^® modeling environment and develop your HDL algorithm. You can use blocks from the HDL Coder library to mimic RAM and ROM blocks on the target device.

To filter the Simulink Library Browser to show only HDL-supported blocks, enter hdllib.

Functions

hdllib Display blocks that are compatible with HDL code generation

Checks

Check for invalid top level subsystem

Blocks

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HDL RAMs

Dual Port RAM System	Dual-port RAM that supports simultaneous read and write operations
Dual Rate Dual Port RAM	Dual Port RAM that supports two rates
HDL FIFO	Store sequence of input samples in first in, first out register
Simple Dual Port RAM System	Simple dual-port RAM that supports simultaneous read and write operations
Single Port RAM System	Single-port RAM that supports sequential read and write operations
True Dual Port RAM System	True dual-port RAM that supports simultaneous read and write operations (Since R2023b)
Simple Tri Port RAM System	Simple tri-port RAM that supports simultaneous read and write operations (Since R2023b)

Topics

Map Matrices to ROM
Map matrices to implement ROM in MATLAB and Simulink.
Use Simulink Templates for HDL Code Generation
Use Simulink model templates for HDL code generation to create efficient hardware designs.
Map HDL FIFO Blocks to UltraRAM Resources on FPGA
Generate HDL code with synthesis attributes that enable UltraRAM inference for an HDL FIFO block on an FPGA. (Since R2026a)

Featured Examples

Getting Started with RAM and ROM in Simulink

Utilize RAM resources in your FPGA design using HDL Coder™.

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