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Hierarchical Designs and Synchronous Hardware Behavior

Create subsystems and hierarchical HDL designs with State Control block

The HDL Coder block library contains many blocks that you can add to your Simulink® modeling environment and develop your HDL algorithm. To model large designs, you can divide your model into subsystems and create hierarchical designs. For synchronous hardware behavior and to generate hardware-friendly HDL code, use the State Control block inside the subsystems.

To filter the Simulink Library Browser to show only HDL-supported blocks, enter hdllib. The blocks listed in this section include those blocks that are only available in the HDL Coder library. Blocks such as Foreach Subsystem and Atomic Subsystem are available in the Simulink library in the Library Browser.

For a filtered list of Simulink blocks supported for HDL code generation, see Simulink Block List (HDL Code Generation).

Functions

hdllibDisplay blocks that are compatible with HDL code generation

Model Settings

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Blocks

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Unit Delay Enabled SynchronousDelay input signal by one sample period when external Enable signal is true
Unit Delay Resettable SynchronousDelay input signal by one sample period when external Reset signal is false
Unit Delay Enabled Resettable SynchronousDelay input signal by one sample period when external Enable signal is true and external Reset signal is false
State ControlSpecify synchronous reset and enable behavior for blocks with state
Synchronous SubsystemRepresent subsystem that has synchronous reset and enable behavior
Enabled Synchronous SubsystemRepresent enabled subsystem that has synchronous reset and enable behavior
Resettable Synchronous SubsystemRepresent resettable subsystem that has synchronous reset and enable behavior

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