# Circuit Design Details Affect PLL Performance

This example shows how to use the Linear Circuit Wizard block to evaluate the effect of loop filter circuit design details on the performance of a phase-locked loop.

Analog circuit imperfections such as circuit element limitations, element value variations, layout parasitics, and device noise can all measurably affect system-level performance. To release a system design for production, you need to evaluate the effects of these analog circuit design details to confirm that the manufactured system meets its performance requirements. For linear, time-invariant analog circuits, the Linear Circuit Wizard block can help by directly solving the detailed circuit equations and packaging the solution in the form of behavioral blocks that will execute efficiently in a Simulink® model.

Open the model `PllAnalogCircuitExample` attached to this example.

The model defines an integer-N single modulus PLL using the basic building blocks from Mixed-Signal Blockset™. The loop filter for the PLL is designed using the Linear Circuit Wizard block. For more information on the PLL model, see Phase Noise at PLL Output.

The PLL Testbench supplies a reference input signal for the PLL. This reference signal is modulated by a PRBS6 phase modulation that is used to measure the closed loop phase noise transfer function of the PLL. The input spectrum is evaluated by a spectrum estimator.

The output spectrum is measured both by the PLL Testbench and by a spectrum estimator like the one used to measure the input spectrum.

The model includes an oscilloscope to measure the PLL loop lock time.

### Initial System Design

The chosen loop filter design is a third order passive loop filter, R2 = `1.33` kΩ, R3 = `17` kΩ, C1 = `13.1` pF, C2 = `144` pF, and C3 = `0.941` pF [1].

The other primary loop design parameters are:

• Reference frequency: `30` MHz

• Prescaler divider ratio: `70`

• VCO sensitivity: `100` MHz/V

• Charge pump output current: `1` mA

The primary circuit impairments are:

• VCO phase noise

• Charge pump imbalance: `0.1` mA

• Charge pump leakage: `0.01` mA

• Reference PRBS6 modulation peak level: `-60` dBc/Hz

To create the loop filter block, start by creating or obtaining a SPICE netlist description of the circuit. This example uses a third order passive loop filter defined in the SPICE netlist file `3rdOrderLoopFilter.sp`. This netlist includes the independent current source Icp to define a current input port and a .print statement to define a voltage output port.

```* Third order passive loop filter * for preliminary system definition Icp N1 0 C1 N1 0 13.1p R2 N1 N2 1.33k C2 N2 0 144p R3 N1 N3 17k C3 N3 0 0.941p .print V(n3 0)```

In the Linear Circuit Wizard block parameters dialog box, set the Circuit design name to `'3rd Order Passive'`, Block name to `'loop filter'`, and Netlist file name to `'3rdOrderLoopFilter.sp'`. Click the Parse netlist file and redefine ports button.

The Port Definition and Device Noise Generators tabs become visible after the netlist has been parsed. Review the content of the Port Definition tab to confirm that the port definitions are correct.

Click the Plot transfer functions button and review the resulting plot.

Click the Build/modify block button and connect the resulting loop filter block between the output of the charge pump and the VCO control voltage.

In the configuration of this model, the charge pump impairments are activated. Therefore, the charge pump defines a fixed step discrete sample time to drive the loop filter. Enabling the impairments also provides the level of detail needed in the later stages of development, at the cost of increased simulation run time. If the charge pump impairments are disabled, then the loop filter can be configured to provide its own sample time. However, a lowpass resampler, such as that used in the Loop Filter block, is required to convert from the variable step discrete sample time of the charge pump without impairments to the fixed step discrete sample time of the loop filter.

Run the simulation.

To plot the PLL output spectrum, you can use the `plotPllOutputSpectrum` helper script attached to this example. The resulting figures highlight the spurious responses at `30` MHz intervals due to the charge pump imbalance, and the output spectrum due to the reference phase modulation. You can create simulations that highlight other effects by modifying the level of these and other impairments.

Add to the simulation the effect of device noise in the loop filter.

Enable and control the addition of device noise to the PLL model using the Device Noise Generators tab in the Linear Circuit Wizard block parameters dialog box. For Circuit Element `R2` and `R3`, select Enable device noise generator and set the Corner frequency (Hz) to `10000` to include a flicker noise corner frequency of `10` kHz.

As soon as you change the definition of the block, for example by enabling device noise, the block mask displays a warning message indicating that the generated block does not reflect the latest changes. Apply the latest changes to the generated loop filter block by clicking the Build/modify block button. The warning message is removed and the block now includes the addition of the device noise.

Click the Plot transfer functions button. The transfer functions now include the transfer function from each device noise source to the output of the loop filter.

Re-run the simulation to include the effect of device noise in the results. To get a clearer evaluation of the effect of the device noise, set the charge pump current impairments to zero while leaving the charge pump impairments enabled, and disable the VCO phase noise. However if you do so, then set the charge pump impairments back to their original value and enable the VCO phase noise for the later sections of this example.

### Practical Circuit Design

Detailed circuit designs that include the effects of circuit element limitations and layout parasitics typically only become available late in the development of a product. At that time, you should incorporate the detailed circuit design of critical components into the system model to confirm that the as-designed system is ready for production.

As a simple example of the types of circuit effects that should be included in the detailed as-designed model, add a charge pump output impedance of `10` kΩ and a VCO control voltage input impedance of `100` kΩ to the third order passive filter model.

The associated SPICE netlist, as supplied in the file `3rdOrderCPLoading.sp` is:

```* Third order passive loop filter * with charge pump output impedance Icp N1 0 Rs N1 0 10k C1 N1 0 13.1p R2 N1 N2 1.33k C2 N2 0 144p R3 N1 N3 17k C3 N3 0 0.941p R1 N3 0 100k .print V(N3 0)```

This schematic and netlist also illustrate an important principle when multiple circuit blocks are to be cascaded. You can cascade multiple linear circuit blocks created by the Linear Circuit Wizard block. The accuracy of your result depends on the accuracy of the modeling of circuit loading at both the input and output of each circuit block.

To evaluate the effect of loop filter circuit loading, change Netlist file name to `'3rdOrderCPLoading.sp'` in the Linear Circuit Wizard parameters dialog box and click the Build/modify block button.

Plot the resulting transfer functions.

Re-run the simulation to include the effect of circuit design details in the results.

The shape of the loop acquisition response has changed. There are more cycle slips during loop acquisition, but much less overshoot. The resulting lock time remains approximately the same as the lock time for the initial system design. Further, there is significantly more noise in the steady state loop filter output, and the additional noise appears to have a more or less constant amplitude.

Plot the PLL output spectrum using the `plotPllOutputSpectrum` helper script. The primary impact of the circuit loading is a substantial increase in the spurious responses.

### Enhanced Circuit Design

In this loop filter design, the last RC section of the loop filter with loading is replaced by a Sallen and Keye active filter. This circuit design introduces a pair of resonant poles with a modest Q factor.

The associated netlist, as supplied in the file `4thOrderActiveFilter.sp`, is:

```* Fourth order loop filter with Sallen and Keye output section Icp N1 0 1e-3 Rs N1 0 10k C1 N1 0 13.1p R2 N1 N2 1.33k C2 N2 0 144p R3 N1 N4 17k C3 N4 N3 0.941p R4 N4 N5 17k C4 N5 0 0.941p E1 N3 0 LAPLACE N5 N3 6.3e7/6.3e4 1 .PRINT V(N3)```

The operational amplifier in this circuit is represented as a voltage controlled voltage source. The open loop response of this amplifier is modeled using the LAPLACE keyword and the expression " `6.3e7/6.3e7 1` ". This expression describes a rational transfer function with a numerator equal to `6.3e7` and the denominator `(s+6.3e4)`. In other words, the amplifier has an open loop DC gain of `1000` and a pole at `10` kHz. This syntax can readily describe transfer functions with more poles and zeros.

In the Linear Circuit Wizard block parameters dialog box, set Circuit design name to `'4th Order Active'` and Netlist file name to `'4thOrderActiveFilter.sp'`.

Plot the transfer functions. Although the low frequency response closely resembles the response of the passive filter with loading, the high frequency response rolls off much more rapidly.

Click the Build/modify block button. The text on the block icon changes to match the revised circuit design name.

Re-run the simulation to evaluate the effect of the active loop filter on the PLL system performance. The loop acquisition response is similar to those for the other cases studied but the loop filter output is much smoother.

Plot the PLL output spectrum using the `plotPllOutputSpectrum` helper script. The output spectrum reflects the improvements to the system performance. Specifically, the out-of-band spurious responses are dramatically reduced and the in-band response remains essentially unchanged.

### References

1. Dean Banarjee. PLL Performance, Simulation, and Design, 4th edition.