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Leverage target hardware instruction set extensions

Instruction sets to generate single instruction, multiple data (SIMD) code

Since R2021b

Model Configuration Pane: Code Generation / Optimization


The Leverage target hardware instruction set extensions parameter specifies the instruction sets to use to generate single instruction, multiple data (SIMD) code for target hardware.


To use this parameter, you must set Device vendor to Intel, AMD, or Generic and Device type to x86-64 (Windows 64), x86-64 (Linux 64), Athlon 64, or MATLAB Host Computer. If you use MATLAB Host Computer, you can choose only instruction sets that are supported by your computer.


SSE2 (default) | None | SSE | SSE4.1 | AVX | AVX2 | FMA | AVX512F

For all targets:

  • None — Does not generate SIMD code.

Instruction sets for GRT-based targets:

  • SSE2

Instruction sets for ERT-based targets:

  • SSE

  • SSE2

  • SSE4.1

  • AVX

  • AVX2

  • FMA

  • AVX512F

The list of instruction sets for ERT-based targets shows the dependency of the instruction sets, where each instruction set depends on the instruction sets that precede it. The code generator loads the selected instruction set and the instruction sets that it depends on. For example, if you select AVX, the code generator loads AVX, SSE4.1, SSE2, and SSE. If you select SSE2 for a GRT-based target or an ERT-based target, the code generator loads SSE2 and SSE.

Recommended Settings

DebuggingNo impact
TraceabilityNo impact
EfficiencyNo impact
Safety precautionNo impact

Programmatic Use

Parameter: InstructionSetExtensions
Type: character vector
Value: 'None' | 'SSE' | 'SSE2' | 'SSE4.1' | 'AVX' | 'AVX2' | 'FMA' | 'AVX512F'
Default: 'SSE2'


  • If you use a custom toolchain for your generated code, you must set Instruction set extensions to None. Instruction set extensions do not support the use of custom toolchains.

Version History

Introduced in R2021b