Complex to Magnitude-Angle

Compute magnitude and/or phase angle of complex signal

• 

Libraries:
Simulink / Math Operations

Description

The Complex to Magnitude-Angle block outputs the magnitude and/or phase angle of the input signal, depending on the setting of the Output parameter. The outputs are real values of the same data type as the block input. The input can be an array of complex signals, in which case the output signals are also arrays. The magnitude signal array contains the magnitudes of the corresponding complex input elements. The angle output similarly contains the angles of the input elements.

Ports

Input

Port_1 — Input signal

scalar | vector | matrix

Complex input signal that the block computes and outputs the magnitude and/or the phase angle.

Limitations

Fixed-point data types are supported only when you set the Approximation method to CORDIC.

Data Types: single | double

Output

Port_1 — Magnitude

scalar | vector | matrix

Output signal that is the magnitude and/or phase angle of the input signal. To choose the output, set the Output parameter.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Port_2 — Radian phase angle

scalar | vector | matrix

Radian phase angle, returned as a real-valued scalar, vector, or matrix.

Dependencies

• To enable this port, set Output to Magnitude and angle or Angle.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Parameters

Output — Magnitude and/or phase angle output specification

Magnitude and angle (default) | Magnitude | Angle

Specify if the output is the magnitude and/or the phase angle in radians of the input signal.

Programmatic Use

Parameter: Output

Type: character vector

Values: 'Magnitude and angle' | 'Magnitude' | 'Angle'

Default: 'Magnitude and angle'

Approximation method — Approximation method

None (default) | CORDIC

Specify the type of approximation for computing output.

Approximation Method	Data Types Supported	When to Use This Method
None (default)	Floating-point	You want to use the default Taylor series algorithm.
CORDIC	Floating-point and fixed-point	You want a fast, approximate calculation.

The block uses these data type propagation rules.

Data Type of Complex Input	Approximation Method	Data Type of Magnitude Output	Data Type of Angle Output
Floating point	None or CORDIC	Same as input	Same as input
Signed, fixed point	CORDIC	fixdt(1, WL + 2, FL) where: WL = input word length of the magnitude + 2 + 1 FL = input fraction length of the magnitude	fixdt(1, WL + 2, FL) where: WL = input word length of the magnitude -3, for best precision for [-pi, pi) FL = input fraction length of the angle
Unsigned, fixed point	CORDIC	fixdt(1, WL + 3, FL) where: WL = input word length of the magnitude + 2 FL = input fraction length of the magnitude	fixdt(1, WL + 3, FL) where: WL = input word length of the angle - 2, for best precision fraction length for range [0, pi/2] FL = input fraction length of the angle

Programmatic Use

Block Parameter: ApproximationMethod

Type: character vector

Values: 'None' | 'CORDIC'

Default: 'None'

Number of iterations — Number of iterations for CORDIC algorithm

11 (default) | positive integer, less than or equal to word length of fixed-point input

Number of iterations the CORDIC algorithm performs, specified as a positive integer-valued scalar. Increasing the number of iterations can produce more accurate results but also increases the expense of the computation and adds latency.

Data Type of Block Inputs	Value You Can Specify
Floating-point	A positive integer. The maximum value is 52 for double or 23 for single.
Fixed-point	A positive integer that does not exceed the word length of the magnitude input or the word length of the phase angle input, whichever value is smaller.

Dependencies

To enable this parameter, set Approximation method to CORDIC.

Programmatic Use

Block Parameter: NumberOfIterations

Type: character vector

Values: positive integer, less than or equal to word length of fixed-point input

Default: '11'

Scale output by reciprocal of gain factor — Scale magnitude of block

on (default) | off

Select this check box to scale the magnitude of the block by the reciprocal of the gain factor (1/CORDIC gain). This value depends on the number of iterations you specify. As the number of iterations goes up, the value approaches 1.647.

This check box is selected by default, which leads to a more numerically accurate result for the complex output, X + iY. However, scaling the output adds two extra multiplication operations, one for X and one for Y.

Dependencies

To enable this parameter, set Approximation method to CORDIC.

Programmatic Use

Block Parameter: ScaleReciprocalGainFactor

Type: character vector

Values: 'on' | 'off'

Default: 'on'

Sample time (-1 for inherited) — Interval between samples

-1 (default) | scalar | vector

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. For more information, see Specify Sample Time.

Dependencies

This parameter is visible only if you set it to a value other than -1. To learn more, see Blocks for Which Sample Time Is Not Recommended.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

Parameter:	SampleTime
Values:	"-1" (default) | scalar or vector in quotes

Block Characteristics

Data Types	double | single
Direct Feedthrough	yes
Multidimensional Signals	yes
Variable-Size Signals	yes
Zero-Crossing Detection	no

More About

CORDIC

CORDIC is an acronym for coordinate rotation digital computer. The Givens rotation-based CORDIC algorithm is one of the most hardware-efficient algorithms available because it requires only iterative shift-add operations (see References). The CORDIC algorithm eliminates the need for explicit multipliers. Using CORDIC, you can calculate various functions such as sine, cosine, arc sine, arc cosine, arc tangent, and vector magnitude. You can also use this algorithm for divide, square root, hyperbolic, and logarithmic functions.

Increasing the number of CORDIC iterations can produce more accurate results, but doing so increases the expense of the computation and adds latency.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™. (since R2026a)

The block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has multi-cycle implementations that introduce additional latency in the generated code. To see the added latency, view the generated model or validation model. See Generated Model and Validation Model (HDL Coder).

HDL Block Properties

General

HDL Property	Description
ConstMultiplierOptimization	Specifies the optimization method for constant multipliers. You can set this property to csd, fcsd, auto, or none. The default setting is none. For more information, see ConstMultiplierOptimization (HDL Coder).
ConstrainedOutputPipeline	Specifies the number of registers to redistribute to the outputs of your design. Use constrained output pipelining to place registers at specific locations and optimize design speed. Distributed pipelining does not redistribute registers placed using constrained output pipelining. The default value is 0. For more information, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Specifies the number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more information, see InputPipeline (HDL Coder).
OutputPipeline	Specifies the number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline (HDL Coder).
LatencyStrategy	Specifies the latency strategy for blocks in the design. You can set the LatencyStrategy to Max, Min, Custom, Custom(PerIteration), or Zero. For fixed-point data types, the block-level setting determines the latency strategy values. The default setting is Max. For more information, see LatencyStrategy (HDL Coder). To enable this property for fixed-point data types, set the Output block parameter to Magnitude and angle, Magnitude, or Angle and set the Approximation method block parameter to CORDIC.
CustomLatency	When you set the LatencyStrategy property to Custom, use this property to specify a custom latency value between Zero and Max. For more information, see LatencyStrategy (HDL Coder).
IterationsPerPipeline	When you set the LatencyStrategy property to Custom(PerIterations), use this property to specify the number of iterations per pipeline stage. For more information, see IterationsPerPipeline (HDL Coder).
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes (HDL Coder).

Latency Values for Fixed-Point Types

When you set the Approximation method block parameter to CORDIC, the block introduces additional latency cycles. The block calculates the latency values based on the Output and Number of iterations block parameters, and the LatencyStrategy HDL block property. This table shows how the block calculates the latency value:

LatencyStrategy Setting	Latency Value (L)
Max	The latency value depends on the Output parameter: When you set Output to Magnitude and angle or Magnitude, the block calculates the latency by using the equation L = N + 4, where N is the value of the Number of iterations parameter. When you set the Output to Angle, the block calculates the latency by using the equation L = N + 3.
Min	The block calculates the latency by using the equation L = 3 + ceil(N / 4).
Custom	Specify a custom latency value between Zero and Max latency value by using the CustomLatency property.
Custom(PerIteration)	Specify the number of pipeline stages per iteration using the IterationsPerPipeline property. The block calculates the latency by using the equation L = 3 + ceil(N / K), where K is the value of the IterationsPerPipeline parameter.
Zero	The latency value of the block is 0.

Optimizations

You can use these HDL Coder optimizations to optimize the speed, area, and I/Os.

Area Optimization

Optimization	Description
Resource Sharing (HDL Coder)	Resource sharing is an area optimization in which HDL Coder identifies multiple functionally equivalent resources and replaces them with a single resource.
Streaming (HDL Coder)	Streaming is an area optimization in which HDL Coder transforms a vector data path to a scalar data path or to several smaller-sized vector data paths.

Speed Optimization

Optimization	Description
Specify Distributed Pipelining Settings (HDL Coder)	Distributed pipelining, or register retiming, is a speed optimization that moves existing delays in a design to reduce the critical path while preserving functional behavior.
Clock-Rate Pipelining (HDL Coder)	Clock-rate pipelining is an optimization framework that allows other speed and area optimizations to introduce latency at the clock rate.
Specify Adaptive Pipelining Settings (HDL Coder)	Adaptive pipelining optimization creates patterns or combination of blocks with registers that can improve the achievable clock frequency and reduce the area usage on the FPGA boards by inserting pipeline registers to the blocks in your design.
Critical Path Estimation (HDL Coder)	To quickly identify the most likely critical path in your design, use critical path estimation. Critical path estimation speeds up the iterative process of finding the critical path. To know blocks that are characterized in critical path estimation, see Characterized Blocks (HDL Coder).

Version History

Introduced before R2006a

R2026a: Specify synthesis attributes for blocks and block output signals

Use the SynthesisAttributes HDL block property to specify the synthesis attributes for the block and its output signals. HDL Coder includes these attributes in the generated HDL code.

R2026a: Scale magnitude of Complex to Magnitude-Angle block

To scale the magnitude of the Complex to Magnitude-Angle block by a factor of (1/CORDIC gain), select the Scale output by reciprocal of gain factor parameter. This value depends on the number of iterations you specify. As the number of iterations goes up, the value approaches 1.647.

R2026a: Generate HDL code with fixed-point data types

The Complex to Magnitude-Angle block now supports HDL code generation with fixed-point input data types. To generate HDL code, set the Output parameter to Magnitude and angle, Magnitude, or Angle, set the Approximation method parameter to CORDIC, and enable the Scale output by reciprocal of gain factor parameter.

R2024b: Complex to Magnitude-Angle block supports fixed-point inputs

Complex to Magnitude-Angle block now supports the CORDIC approximation method. This method allows fixed-point inputs at input Port_1. To select the CORDIC method, set the new Approximation method parameter to CORDIC.

When you select the CORDIC method, the block icon updates. The new parameter, Number of iterations, lets you define the number of iterations for the CORDIC algorithm.