Revisione dei risultati di analisi
Utilizzare Simulink® Design Verifier™ per registrare e rivedere i risultati di analisi e generare report di analisi. È possibile generare input di test ed esportarli in nuovi casi di test in Simulink Test™.
Funzioni
sldvloadresults | Load Simulink Design Verifier analysis results for model |
sldvhighlight | Highlight model using data from Simulink Design Verifier analysis |
sldvreport | Generate Simulink Design Verifier report |
sldvsimdata | Get simulation data in Dataset format |
sldvruntestopts | Generate simulation or execution options for sldvruntest or
sldvruncgvtest |
sldvruntest | Simulate model by using input data |
sldvharnessopts | Default options for sldvmakeharness |
sldvmakeharness | Generate harness model |
sldvmergeharness | Merge test cases and initializations into one harness model |
sldvruncgvtest | Invoke Code Generation Verification (CGV) API and execute model |
Argomenti
- Highlight Results on the Model
Describes highlighting of analysis results on the model.
- Review Results
Describes the different parts of a Simulink Design Verifier report.
- Manage Simulink Design Verifier Harness Models
Describes a basic harness model.
- Manage Simulink Design Verifier Data Files
Describes the contents of a Simulink Design Verifier data file.
- Review Analysis Results
Review analysis results in the Simulink Design Verifier Results Summary window.
- Export Test Cases to Simulink Test
Describes how to generate test cases in Simulink Test using Simulink Design Verifier analysis results, which can be generated by property proving, design error detection, and test case generation.
- Generate and Export Tests from Requirements Table Blocks
Automate test generation and execution in models that contain Requirements Table blocks.
- Filter Objectives by Using Simulink Design Verifier Filter Explorer
Describes the filtering of objectives by using Analysis Filter explorer.
- Inspect Test Generation Objectives by Using Model Slicer
Inspect Test Generation Objectives using Model Slicer.
Esempi in primo piano
Simulate Harness Model with Signal Editor Inputs Block
Generate model coverage report by simulating the test harness model with the Signal Editor Inputs block. You can simulate a single test case or counterexample by selecting the active scenario in the Signal Editor dialog box. For more information see, Simulate Harness Model by Using the Signal Editor Inputs Block.
Defining and Extending Existing Tests Cases
How Simulink® Design Verifier™ can extend test cases with additional time steps to efficiently generate complete test suites.
Extend an Existing Test Suite
Use Simulink® Design Verifier™ to extend an existing test suite to obtain missing model coverage.
