Memory Traffic Generator
Generate traffic towards memory controller
SoC Blockset / Memory
When connected to a memory controller, the Memory Traffic Generator block generates read or write requests to the memory, acting as a master. Use this block to model the impact that a master’s memory accesses has on your algorithm without explicitly simulating the behavior of that master. You can also use the Memory Traffic Generator block to characterize performance of your memory subsystem under varying levels of memory access contention.
To model memory contention, the Memory Traffic Generator block gains memory access, competes in arbitration, and releases access. The Memory Traffic Generator block does not actively read or write from memory.
burstDone — End of burst and access to memory
burstReq — Request memory access from memory controller
Request type — Choose between write or read request
Writer (default) |
Choose between a write or read request type for the block to generate.
Total burst requests — Number of burst requests to generate
100 (default) | integer greater than 1
Generate recurring traffic patterns by setting this value to an integer greater than one.
Burst size (bytes) — Size of generated burst transactions
256 (default) | scalar
Specify the size of each burst transaction in bytes. This parameter, along with the width of the datapath (as configured in the configuration parameters), controls the burst length.
Time between bursts (s) — Simulation time between burst requests
1e-6 (default) | time, in seconds
Specify simulation time between burst requests, in seconds.
To enable this parameter, clear the Allow simulation only parameters parameter.
If you cleared Allow simulation only parameters and this parameter is not visible – click Apply at the bottom of the Block Parameters dialog box.
Allow simulation only parameters — Configure additional parameters for simulation only
on (default) |
Select this parameter to enable configuration of simulation-only parameters.
First burst time — Simulation time for initial burst request
10e-6 (default) | time, in seconds
Specify simulation time, in seconds, for sending the initial burst request. This value must be a positive real scalar.
To enable this parameter, select Allow simulation only parameters parameter.
Random time between bursts (s) — Range of simulation time for recurring requests
[1e-6 1e-6] (default) | vector of the form [min
Specify the range of simulation time between burst requests with a vector of the form [min max].
min is the minimum time, in seconds, between recurring requests.
max is the maximum time, in seconds, between recurring requests.
min and max must be nonnegative, and max must be greater than min.
To specify a deterministic rate, set the minimum and maximum time between requests to the same value. If you want reproducible randomization, specify a seed in the configuration parameters, on the Hardware Implementation pane. For more information on setting the seed value, see Task and memory simulation.
To enable this parameter, select the Allow simulation only parameters parameter.
Wait for burst done — Wait for burst-done signal before generating next request
off (default) |
Select this parameter to wait for a burst-done signal from the previous burst before generating the next burst request. Clear this parameter to generate burst requests regardless of other master traffic. To get a known data rate, clear this parameter.
Enable assertion — Enable verbose information
off (default) |
Select this parameter to view diagnostic messages when the Traffic Generator block drops a packet. Clearing this parameter enhances simulation performance.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool. See Generate SoC Design.