Stream data to processor algorithms
SoC Blockset / Processor I/O
The Stream Read block streams data from shared memory in the memory channel to your processor algorithm. In simulation, a timer-driven or event-driven task subsystem contains the Stream Read block. The data signals from the Memory Channel block connect to the Stream Read block. Following a write to the shared memory, the Memory Channel notifies the Task Manager block of the write event. The Task Manager block then triggers the event-driven subsystem containing the Stream Read block and associated algorithm.
When developing or analyzing the software side of an SoC application, the Stream Read block can be connected to an IO Data Source block. In this configuration, the IO Data Source block provides either previously recorded or artificial data, enabling a more directed simulation of the software and processor side of the application, without need to explicitly model the hardware and memory interactions.
data— Data frame from shared memory
This port emits a data frame read from shared a region of shared memory defined in the Memory Channel block.
valid— Valid frame data
A flag indicating a valid data frame read from the memory channel.
msg— Data message from memory
This message port receives data messages from the connected Memory Channel or IO Data Source block. The messages process when the Task Manager block triggers the task containing the Stream Read block. For more information on messages, see Messages (Simulink).
This port appears when
Simulation output is set to
From input port.
Device name— File name of IP core device
ip:s2mm0(default) | character array
Enter the name and channel of the IP core on the FPGA as a colon separated list.
Output data type— Data type of IP core
Enter the data type used by the memory channel.
Samples per frame— Size of data vector read from IP core
1024(default) | positive scalar integer
Enter the size of the data vector read from the memory channel.
Number of buffers— Number of data buffers
16(default) | positive integer
Enter the number of data frame buffers in physical memory.
Enable event-based execution— Enable event-driven task execution
To use this block in event-driven task subsystems, select this parameter. To use this block in timer-driven task subsystems, clear this parameter.
When Enable event-based execution is selected, this block reads from the Memory Channel each time a write occurs to that shared memory region. When Enable event-based execution is cleared, the block reads the data in the shared memory region at each sample time.
Sample time— Sample time in seconds
-1(default) | positive scalar
Enter the sample time used by the timer-driven task subsystem when the Enable event-based execution is cleared.
To automatically generate C code for your design, and execute on an SoC device, use the SoC Builder tool. See Generate SoC Design. You must have an Embedded Coder® license to generate and execute C code for your SoC device.
SoC Builder implements the Stream Read, Memory Channel, and Task Manager blocks with FPGA and processor IPs that use the AXI4-stream communication protocol. The AXI4-stream protocol uses a direct memory access (DMA) to read a data vector to a shared region on the external memory. This protocol allows for high-speed streaming of data between the FPGA and the embedded processor through external memory. This diagram shows a generalized representation of the generated code implementation.