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LDPC Encoder

Encode quasi-cyclic low-density parity-check code

Since R2023a

  • LDPC Encoder block

Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The LDPC Encoder block implements a quasi-cyclic low-density parity-check (QC-LDPC) encoder with hardware-friendly control signals. The block accepts data bits and a stream of control signals and outputs encoded bits, a stream of control signals, and a signal that indicates whether the block is ready to accept new inputs.

The block supports scalar inputs with a specified parity-check matrix and block size. The block also supports lower-triangular or upper-triangular, dual-diagonal, and mixed-diagonal parity-check matrices. The block supports LDPC codes of circulant weight 1. For more information, see Parity-Check Matrix.

You can use this block to develop a standard-based or generalized transmitter that uses a QC-LDPC for forward error correction (FEC) coding. The block provides an architecture suitable for HDL code generation and hardware deployment. See Algorithms.

Ports

Input

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Data bits, specified as a scalar. The input data length must be (NM) x Z, where M is the number of rows in the parity-check matrix, N is the number of columns in the parity-check matrix, and Z is the block size.

Data Types: Boolean

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

  • start — Indicates the start of the input frame

  • end — Indicates the end of the input frame

  • valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

Output

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Encoded data bits, returned as a scalar.

Data Types: Boolean

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

  • start — Indicates the start of the output frame

  • end — Indicates the end of the output frame

  • valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

The block sets this signal to 1 when the block is ready to accept the start of the next frame. If the block receives an input start signal while nextFrame is 0, the block discards the frame in progress and begins processing the new data.

For more information, see Using the nextFrame Output Signal.

Data Types: Boolean

Parameters

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Specify a QC-LDPC parity-check matrix of size M-by-N, where M is the number of rows in the parity-check matrix and N is the number of columns in the parity-check matrix. N must be in the range [4, 128]. M must be less than N and must be in the range [3, N–1]. The last M columns of the parity-check matrix must be invertible in GF(2).

To learn more about the supported parity-check matrices, see Parity-Check Matrix.

Specify the block size. The block size must be an integer in the range [2, 512].

More About

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Algorithms

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This figure shows the architecture block diagram of the LDPC Encoder block.

The Input Controller block reads and writes input data to the Input RAM block and enables the encoding after writing the entire frame to input RAM. The Parity-check matrix block consists of specified parity-check matrix values and provides shift values to the Shifter block. The Alpha RAM block stores the shifted output. The Parity Controller block calculates parity bit sequences and stores them in the Parity RAM block. The Mux block multiplexes and serializes the bits from the Input RAM and Parity RAM blocks.

LDPC Encoder Block Architecture

Extended Capabilities

Version History

Introduced in R2023a

See Also

Functions

Blocks