Modifying the QPSK RX for TDD for hw/sw design in ad9361
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The current model provided in: https://www.mathworks.com/help/supportpkg/xilinxzynqbasedradio/ug/hw-sw-co-design-qpsk-transmit-and-receive-using-analog-devices-ad9361-ad9364.html works for FDD mode. The QPSK RX moduel found in the design has been assigned a threshold value of 16 but in TDD this value tends not to work as when we switch from no signal to a signal it the QPSK RX valid out signal becomes valid even if there is no valid data. It does not check against the barker code therefore giving wrong output. Is there anyway I can fix this or how should i change the threshold value?
Kranti Balaga on 24 Nov 2021
The Model you are referring is not supported for discrete valid of inputs, and the receiver is expecting always continuous data. Suppose if you provide the RxValid_In low, the core receiver takes the previous valid data when you provide the valid low and it results wrong data in to the receiver. You can see Enabled Delay in zynqRadioHWSWQPSKAD9361AD9364SL/HDL_QPSK/HDLRxIPCore
Also, as the Threshold is fixed and it is not depends on the input signal, it is will not work for your usecase.
We upgrade the receiver core model, where the threshold is calculated dynamically based on the input signal. I think this will help for your usecase. Here also receiver expects continuous data, but, you can simply modify for your usecase
Check the example here HDL QPSK Transmitter and Receiver - MATLAB & Simulink (mathworks.com)