HDL Code Generation (Verilog) for a 2-D Lookup Table
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I am trying to implement a control procedure which has to map to a value based on two measurements. I have decided to use 2-D lookup table for this purpose.
The simulink lookup-table block is working as per my expectations. However, I need to implment the design on a FPGA and in need of the .v file. I have tried generating code and seems to work, but I am not sure of the details to be considered. Also, I am not aware of how to use floting point while generating code.
I would be really helpful to get a step by step procedure to generate the HDL code for the lookup table.
Joel Van Sickel on 30 Dec 2021
you can go through examples like this for generating hdl: https://www.mathworks.com/help/hdlcoder/gs/example-generating-hdl-code-from-a-simulink-model.html
if you are having issues, try dragging the lookup table block from the hdl coder library instead of the normal one if you haven't done that already. There is nothing different for generating hdl code for a lookup table than other simulink blocks. However, there may be limitations on what lookup table options you can use, so you need to read any warning messages or errors to see if you are using an unsupported feature.