Can the HDL FFT be made to process a vector that is greater than 64?

I have the HDL coder FFT block and I want to send it twice the max vector size (i.e. 128 instead of 64). Is there an already established way to complete this so I don't have to reinvent the wheel?

[Bharath Venkataraman]

A clarification: Do you want the FFT to process 128 samples per clock? That is a large amount of samples to process per clock and would be difficult to fit into a device (especially routing 128 samples * Number of bits per sample).

[denkvakva]

Yes, the goal is 128 samples per clock cycle while not changing the clock speed.

[Bharath Venkataraman]

I suggest reaching out to MathWorks support with this question.

Answer 1

[Sahas Marwah]

Hi @denkvakva,

Assuming that, you are using the HDL coder FFT block in Simulink and need the input vector size to be twice the maximum which is 64.

There are a few indirect ways you can do this:

1. One way is to split the input vector into multiple smaller vectors that can be processed separately by multiple FFT blocks. This can be achieved using MATLAB functions such as reshape, or mat2cell. You can then combine the outputs of each FFT block to generate the final output.

2. Use a streaming interface for the FFT block, which allows you to process large input vectors in smaller chunks. This can be done by setting the 'Streaming Architecture' parameter of the FFT block to 'On', which enables the use of serial or streaming interfaces for the block.

You can visit these documentation pages for more help on the above steps:

https://in.mathworks.com/help/wireless-hdl/ug/hdl-implementation-of-a-variable-size-fft.html -- HDL Implementation of Variable-Size FFT

https://www.mathworks.com/help/dsphdl/gs/generate-hdl-code-for-fft-hdl-optimized-block.html -- Implement FFT Algorithm for FPGA

https://www.mathworks.com/help/dsphdl/ref/fft.html -- FFT Computation