The obtained FPGA (Hardware-in-the-loop) output waveform is inconsistent with Simulink simulation results.
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ZhiHao
il 17 Set 2023
Commentato: Kiran Kintali
il 13 Ott 2023
We combined Xilinx Zynq-7000 ZC702 Evaluation Kit and SImulink for HIL (Hardware-in-the-loop) simulation. The specific process is as follows: 1. Transform the power electronic model built in Simulink into a state-space model. 2. Run the state space model through HDL workflow to generate bit flow, and select IPcore mode. 3. Download the bitstream to the development board. Finally run and find the obtained FPGA output waveform is inconsistent with Simulink simulation results.
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Kiran Kintali
il 17 Set 2023
Modificato: Kiran Kintali
il 25 Set 2023
Using Simulink / Simscape for modeling and targeting a State space model to FPGA hardware is well established HDL Coder workflow. Please find the attached examples.
Can you please reach out to tech support for additional debugging on this issue?
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Kiran Kintali
il 13 Ott 2023
Those are really old versions than the latest MATLAB R2023b release. You can check the tested tool versions here and reach out to tech support.
https://www.mathworks.com/help/releases/R2023a/hdlcoder/gs/language-and-tool-version-support.html
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