HDL Optimized FFT Does Not Yield the Same Results As FFT

I am trying to take the FFT of a GPS C/A Code for a specific satellite. For FFT block, I directly feed the C/A Code vector (1023x1 vector) to the FFT Block. For HDL Optimized FFT, I write the vector data to a Block Ram. When the HDL Optimized FFT is ready (ValidOut is equal to 1) I start reading the data from the RAM, and feed the data to the block one sample by one sample.

Here is the model:

Here is the output comparison:

A closer look:

It seems like there is a delay of 6 samples between the outputs even though the values do not match 100 percent. What might be the reason for that? In addition, when the ValidOut of HDL FFT block is 1, the FFT result is still zero. What is the reason for that? I read the data from the ram continuously. When the read address is 1023, in the next iteration it becomes 1. So a circular-wise reading occurs. And at the first cycle (reading from 1 to 2023) the output is zero. After this cycle, the output is as in the figure.

[Tom Richter]

Hi Kaan,

First of all, we need to understand you problem a bit more. You write about a 1023 value vector, however, only powers of two vectors are allowed in HDL Optimized FFT (1024). Even if you pad with zero it will be a bit different. The FFT block can handle also 1023.

Yes, there is a latency of the HDL Optimized FFT which is stated on the block once the model is updated (2107 if I read correctly). You can just add a delay block after the FFT block with the same value for a better comparision.

BTW, the HDL Optimized FFT block is always ready in your setup. Would you use Burst Mode there would be an additional ready signal which shows that the algorithm is still busy. In your case you can feed in data the whole time and the block outputs with the specified latency. Valid data is indicated by the Valid Out and should start 2107 cycles after feeding in the first input sample + valid in = true.

What are the data types you use for the FFT and the HDL FFT?

Best regards,

Tom

[Kaan]

Hi Tom, thank you so much for your throughout answer. I was using double type for FFT input, and uint16 for RAM address.

Answer 1

[Bharath Venkataraman]

I would log the data and valid signals going into the HDL FFT to see if the data is the same as that going into the non-HDL FFT.

I suspect what is happening is that there are a bunch of zero values being sent in to the HDL FFT initally since the valid input signal into the HDL FFT is set high all the time while the data itself goes through the RAM and takes a few cycles to show up.

[Bharath Venkataraman]

Here is a simple example of the DSP FFT and the HDL FFT in a single model. Run the MATLAB script to simulate and then compare frame 1 output of the DSP and HDL FFTs. As you can see, the two FFTs are fairly similar in their numerics.

The MATLAB script compares the input as well as the output to make sure that things are in order.