Hi xiaodong,
I am assuming that your model contains a LUT block to process input data and a pipeline register block at the output of the LUT. A similar example model to the model you are referring to is available in the following documentation:
The example model has two subsystems with a lookup table (LUT):
- “LUT_BRAM”: This subsystem is already optimized with a pipeline register block at the output of the LUT. When synthesized, the LUT is efficiently mapped to the block RAM without any pipeline insertions.
- “LUT”: This subsystem has a LUT with no optimizations done to it.
The message about the “LUTMapToRAM” option is a diagnostic message rather than a warning. It appears in the “Diagnostic Viewer” tab when HDL code is generated for the “LUT” subsystem with necessary pipeline insertions to optimize the LUT output. The message states:
- The “Map lookup tables to RAM” option in the “HDL Code Generation” > “Optimization” > “Pipelining” tab in the “Model Configuration Parameters” dialog box has been enabled.
- This option provides optimization to the “LUT” subsystem using pipeline insertions by adding a “Delay” block labelled “Pipeline Register” to the output of the LUT.
- The output delay allows the HDL Coder to efficiently map the LUT to the block RAM.
The option must be checked regardless of presence of the “Delay” block to map the LUT to the block RAM.
The message about the “LUTMapToRAM” option will disappear from the Diagnostic Viewer if the “Delay” block is inserted beforehand at the output of the LUT in the “LUT” subsystem, just like the one inserted in the “LUT_BRAM” subsystem. The “LUT” subsystem is now modelled to map to block RAM efficiently and pipeline insertion is not required anymore.
The modified example model to validate this process has been attached to this answer. You can follow the modelling pattern used either in the documentation or the attached model to verify that the message indeed disappears in your model.
I hope this answers your query.
