Not able to Build FPGA BitStream for Simscape example model Half Wave Rectifier
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Hello Everyone ,
I am referring to link : https://www.mathworks.com/help/hdlcoder/ug/simscape-hil-speedgoat-fpga-io-modules.html,
in which when trying to generate FPGA bitstream for 'gmStateSpaceHDL_sschdlexHalfWaveRectifierEx/Simscape_system/HDL Subsystem' , the simulink doesnot proceed from Section 4.2 , I have waited for around 3hrs and followed all steps mentioned in above link
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1682171/image.png)
Kindly help me resolve the issue
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Kiran Kintali
il 29 Apr 2024
What version of synthesis tools AMD/Xilinx Vivado are you using currently?
The demo should work as expected in 23a. Have you also tried using 24a? Is it the same behavior? The screenshot shows you are stuck in Vivado bitstream step; it may unlikely be an issue on the HDL Coder side.
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Kiran Kintali
il 1 Mag 2024
Can you reach out to tech support? I am not sure if this could be Vivado version related issue.
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