How to generate simulink model from multiple verilog codes?
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Jaykishan Solanki
il 3 Lug 2024 alle 7:01
Commentato: Jaykishan Solanki
il 4 Lug 2024 alle 6:07
I am trying to generate simulink model from almost 175 verilog files. Using importhdl it always shows some error whether i try using folder, subfolder, path or filenames. Is there any way to fix it?
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Kiran Kintali
il 3 Lug 2024 alle 19:35
Please note HDL Coder only supports a subset of synthesizable HDL suitable for a Simulink representation in this import process. You may be running into obvious limitations in the workflow. Not all Verilog/VHDL is importable to Simulink.
Added some intro slides on the importhdl command.
Can you share some more details? It is unclear the issues you are facing. Do not hesitate to reach out to tech support support@mathworks.com
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