Troubleshooting Signal Logging in SDI for FPGA Outputs in Speedgoat Motion Control HDL I/O Blockset

In pwm_example_hdlc.slx example from Speedgoat Motion Control HDL I/O Blockset v1.0 (R2024b). I want to view logged signals in SDI. There are PWM and CAP signals in the example which are set to logging.

I succesfully generated bitstream and run example on Speedgoat P3 Perfomance. The hardware generates PWM signals as expected (confirmed with oscilloscope). However, the SDI does not have any signal available during or post model execution.

During model build the following warning(s) is issued:

Warning: Unable to instrument 'gm_pwm_example_hdlc_slrt/DUT PWM and CAP/DataTypeConversion:1': Unable to stream signal

'gm_pwm_example_hdlc_slrt/DUT PWM and CAP/DataTypeConversion:1'. Possible reasons include:

(1) Signal is not available in application.

(2) Signal does not use globally accessible memory in application.

(3) Signal connects to a MessageSend block.

(4) Signal has inherited sample time.

(5) Signal is discontiguous.

For more suggestions to resolve this issue, see Troubleshoot Signals for Streaming or File Log logging.

I followed the advice given in Troubleshoot Signals for Streaming or File Log logging and in this post:

• added test point
• added Signal Copy Block
• made PWM_A signal globally accessible

But the issue persist and no data appears in SDI (external mode, command line, slrtExplorer).

If I add the rate transition block, the signal appear in SDI, however the value is 0 (Output port sample time is 1e-4s), whereas PWM perion is 1e-3s.

If I add sine generator block in the model and log its output, this sine output signal appears in SDI as expected.

What can be the reason that the outputs from FPGA cannot be visualized in the model?

Answer 1

[Kiran Kintali]

Klemen, Thanks for reporting this. Our support team at Speedgoat is reviewing the issue and respond here shortly.

Answer 2

[Dimitri MANKOV]

Hi Klemen,

Thanks for asking! Just for future reference, please note that you can always reach out with new questions and support requests to the entire Speedgoat Support team at [e-mail] or using the Speedgoat support web-form. It is usually the quickest way to get assistance if you are struggling with example models provided by Speedgoat.

Coming back to your question: the signal you are trying to log is a "remnant" coming from the source model. As explained in a previous MATLAB Answers post here, such ports assigned to physical input/output interfaces of your FPGA module are not cleaned up automatically in the model generated by the HDL Workflow Advisor after your FPGA logic design is translated into a configuration file (bitstream). If you deploy this model on the hardware, signals coming form such ports will most likely stay at zero (you can explore what they are mapped to in the generated model by going under the mask of the FPGA subsystem). You can cleanup all blocks and connections from terminated input ports and from grounded output ports using the function "speedgoat.hdlc.cleanGeneratedModel", more information about it here:

https://www.speedgoat.com/help/hdlcoder/page/refentry_sgapi_hdlc_clean_generated_model

I hope this is helpful!

Dimitri

[Klemen D]

Thank you.