Hi, I'm trying to generate a VHDL code from Hdl coder. My function file is like below.

 function[a]=frfunc(x,y,c)
  a=0;
 for i=0:c
   a(i)=x(i)+y(i);
 end
 end

The error was

"Found an unsupported unbounded loop structure at '...'. This loop may be user defined or automatically generated due to the use of specific vector expression or function".

so how to write a for loop whose limit(i.e 'c') is read from the test bench file.

[Walter Roberson]

You appear to be indexing at 0, which would not lead to the message you are seeing but would lead to other errors.

You should be using initializing a to the appropriate size, such as

a = zeros(1, c+1);

Answer 1

[Tim McBrayer]

You will need to use some other method of informing your loop when to stop iterating. Hardware designs require fixed sizes for both loops and data structures. Otherwise, how can the size of registers, amount of RAM, etc., be determined?

One possibility is to declare your array a to have some maximum size. Then you can replace your count size 'c' with a data valid strobe coming from your testbench. When the strobe is '1', process the next pair of inputs. When it's low, do nothing.