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buffer block inside enabled subsystem

Asked by DEEKSHA GUPTA on 8 Apr 2018
Latest activity Answered by Bharath Venkataraman on 9 Apr 2018
I have created model for finding 512 point FFT in simulink,FFT is processing 16 samples at a time(16*1),within that model i have used enabled subsystem and within that enabled system buffer block is used to buffer 512 samples but while doing HDL code generation it is showing an error "Simulink Block Warnings/Errors fft512V16/mainsystem/Enabled Synchronous Subsystem/Deserializer1D Error: Illegal block in enabled subsystem. fft512V16/mainsystem/Enabled Synchronous Subsystem/Enable Error: All ports of an enabled/triggered subsystem must have the same sample rate for HDL code generation. " I have attached a snapshot of my model,plz try to fix asap.

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Answer by Tim McBrayer on 9 Apr 2018

As the error message states, all ports of an enabled subsystem must be the same rate, for HDL code generation. From your image I can see that the inputs are at a rate displayed in red (the fast rate), while the outputs are displayed in green (a slower rate).
The message also states that you have a Deserializer in the enabled subsystem. Since the Deserializer is inherently multi-rate, this might be causing the issue.

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Answer by Bharath Venkataraman on 9 Apr 2018

What is the purpose of using the buffer block in an enabled subsystem? You cannot really have 512 samples coming out of an FPGA (there aren't enough pins). What you likely want to do is to send out 16 samples at a time (if you can) and then collect them outside the FPGA.

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