VHDL code generation and avoiding magic numbers?
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Hi,
I would like to avoid magic numbers in my auto-generated VHDL code. Is there a way to neatly generate a pkg.vhdl file of constants using a Simulink model and the HDL Coder tool? Alternatively, is there is a best practice model architecture for generating global constants?
Thanks for reading!
Sara
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Kiran Kintali
il 14 Dic 2019
Currently HDLCoder does not have the capaibility of generating all constants into pkg file. Please reach out to support@mathworks.com to create an enhancement request.
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