Thank you for your question.
I recommend you use a Test Objective block, which you can use to define a desired value for any signal in your model. You can also use the Test Condition block to constrain other signal values. Simulink Design Verifier will try to generate any test that achieves the objective of reaching the value defined within the Test Objective, and will constrain other signals accordingly based on the Test Conditions.
Try the following example for Test Objective blocks:
A Test Condition block can also be used to constrain the rate of change of a signal, which is commonly required. This can be achieved using standard Simulink blocks, such as in this simple example:
The "Expected Output" option will actually create a cell array of vectors containing the output values of the model outputs after the tests are generated. This is a bit confusing, and I will take this feedback to our Documentation team.