Error with cosimulation on tunable parameters

Hello all!

I'm having trouble with conducting FPGA In the Loop. I'm getting this error regarding cosimulation and tunable parameters. Do you know of a solution or a bypass? The objective is to do a FPGA in the loop simulation of a field oriented control based current controller.

Answer 1

[Kiran Kintali]

This is a limitation in the cosimulation test bench generation.

Can you consider using stand-alone testbench with HDL Simulator?

[kimi]

Ok. Is there no way for me to integrate the Zedboard? Can I do FPGA data capture?

Answer 2

[Kiran Kintali]

https://www.mathworks.com/help/supportpkg/xilinxzynqbasedvision/ug/fpga-targeting-workflow.html

yes, You can target zed board using HDL Coder. FPGA data capture is another good way to capture signals. please contact [e-mail]