Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.
3 visualizzazioni (ultimi 30 giorni)
Mostra commenti meno recenti
After compiling an FPGA in the loop simulink model with VHDL Verifier for Xilinx or Altera devices the new model with the FIL object appears. On windows, a new terminal shows that a new bitstream is being generated but on Ubuntu 18.05, no file is ever created. Am i missing a configuration step?
1 Commento
Cau Tran
il 11 Ago 2022
I also had this problem. Can anyone give me advice for this one?
FIL does not generate the bitstream file.
Risposte (1)
YP
il 21 Nov 2022
Can you check if xterm is installed?
FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html
0 Commenti
Vedere anche
Categorie
Scopri di più su FPGA, ASIC, and SoC Development in Help Center e File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!